Twister AT System Board Manual
Chapter 4: The BIOS Setup Utility
44
8-Bit/16-Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles be-
tween PCI-originated I/O cycles to the ISA bus. This
delay takes place because the PCI bus is so much faster
than the ISA bus. These two fields let you add recovery
time (in bus clock cycles) for 16-bit and 8-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of system memory for the ISA
adapter ROM. When this area is reserved, it cannot be
cached.
PCI Passive Release
When Enabled, CPU to PCI bus accesses are allowed
during passive release. Otherwise, the arbiter only ac-
cepts another PCI master access to local DRAM.
PCI Delayed Transaction
The chipset has an embedded 32-bit posted write buffer
to support delay transaction cycles. Select Enabled to
support compliance with PCI specification version 2.1.
Summary of Contents for Twister AT Pentium
Page 14: ...Twister AT System Board Manual Chapter 1 Quick Installation 12 ...
Page 60: ...Twister AT System Board Manual Chapter 4 The BIOS Setup Utility 58 ...
Page 66: ...Twister AT System Board Manual Appendix A Technical Information 64 ...
Page 70: ...Twister AT System Board Manual Appendix B POST Messages 68 ...