Tigercat System Board Manual
Appendix C: Beep and POST Codes
66
Code
Beeps
POST Routine Description
02
Verify Real Mode.
04
Get CPU type.
06
Initialize system hardware.
08
Initialize chipset registers with initial POST values.
09
Get in POST Reg.
0A
Initialize CPU registers.
0C
Initialize cache initial POST values.
OE
Initialize I/O.
OF
Initialize the localbus IDE.
10
Initialize Power Management.
11
Load alternate registers with initial POST values.
12
Jump to UserPatch0.
14
Initialize keyboard controller.
16
2-2-3
BIOS ROM checksum.
18
8254 timer initialization.
1A
8237 DMA controller initialization.
1C
Reset Programmable Interrupt Controller.
20
3-1-1
Test DRAM refresh.
22
3-1-3
Test 8742 Keyboard Controller.
24
Set ES segment register to 4 GB.
28
Autosize DRAM.
2A
Clear 512K base RAM.
2C
3-4-1
Test 512K base address lines.
2E
3-4-3
Test 512K base memory.
32
Test CPU bus-clock frequency.
34
Test CMOS RAM.
35
Initialize alternate chipset registers.
37
Reinitialize the chipset (MB only).
38
Shadow system BIOS ROM.
39
Reinitialize the cache (MB only).
3A
Autosize cache.
