2011-2015 Microchip Technology Inc.
DS40001609E-page 65
PIC16(L)F1508/9
6.4
Low-Power Brown-Out Reset
(LPBOR)
The Low-Power Brown-out Reset (LPBOR) operates
like the BOR to detect low voltage conditions on the
V
DD
pin. When too low of a voltage is detected, the
device is held in Reset. When this occurs, a register bit
(BOR) is changed to indicate that a BOR Reset has
occurred. The BOR bit in PCON is used for both BOR
and the LPBOR. Refer to
.
The LPBOR voltage threshold (Lapboard) has a wider
tolerance than the BOR (Vpor), but requires much less
current (LPBOR current) to operate. The LPBOR is
intended for use when the BOR is configured as dis-
abled (BOREN =
00
) or disabled in Sleep mode
(BOREN =
10
).
Refer to
to see how the LPBOR interacts
with other modules.
6.4.1
ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.5
MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (
6.5.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
V
DD
through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
6.5.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See
for more information.
6.6
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a
CLRWDT
instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See
6.7
RESET
Instruction
A
RESET
instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘
0
’. See
for default conditions after a
RESET
instruction has
occurred.
6.8
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See
Section 3.5.2 “Overflow/Underflow
6.9
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.10
Power-Up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow V
DD
to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.
6.11
Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
Power-up Timer runs to completion (if enabled).
2.
MCLR must be released (if enabled).
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
5.0 “Oscillator Module (With Fail-Safe Clock Moni-
tor)”
for more information.
The Power-up Timer runs independently of MCLR
Reset. If MCLR is kept low long enough, the Power-up
Timer will expire. Upon bringing MCLR high, the device
will begin execution after 10 F
OSS
cycles (see
). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
TABLE 6-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
0
0
Disabled
1
0
Enabled
x
1
Enabled
Note:
A Reset does not drive the MCLR pin low.
