MIC24045 Internal Registers
2017 Microchip Technology Inc.
DS50002619A-page 34
REGISTER C-1:
STATUS: STATUS REGISTER (ADDRESS 0H)
R-0
R-0
R-0
R’0’
R-0
R’1’
R-1
R-0
OCF
ThSDF
ThWrnF
Reserved
EnS
Reserved
Reserved
PGS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
RC = Read-then-clear bit
bit 7
OCF:
Over-Current Flag bit. OCF is set high whenever an overcurrent event occurs. Latched.
bit 6
ThSDF:
Thermal Shutdown Flag bit.
ThSDF is set high whenever a Thermal Shutdown occurs.
Latched.
bit 5
ThWrnF:
Thermal Warning Flag bit. ThWrnF is set high whenever a Thermal Warning occurs.
Latched.
bit 4
Reserved:
Flag bit. Always read as zero.
bit 3
EnS:
Enable Pin Status bit. EnS reflects the logic value present on pin EN. Nonlatched.
bit 2
Reserved:
Status bit.
Always read as ‘
1
’.
bit 1
Reserved:
Default status at POR is ‘
1
’ (no faults detected).
bit 0
PGS:
Power-Good Status bit.
PGS reflects the logic value present on pin PG. Nonlatched.
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