Microchip Technology MCP3422, Manual

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©
2008 Microchip Technology Inc. DS22088B-page 13
MCP3422/3/4
4.0 DESCRIPTION OF DEVICE
OPERATION
4.1 General Overview
The MCP3422/3/4 devices are differential multi-chan-
nel low-power, 18-Bit Delta-Sigma A/D converters with
an I
2
C serial interface. The devices contain an input
channel selection multiplexer (mux), a programmable
gain amplifier (PGA), an on-board voltage reference
(2.048V), and an internal oscillator.
When the device powers up (POR is set), it automati-
cally resets the configuration bits to default settings.
Device default settings are:
• Conversion bit resolution: 12 bits (240 sps)
• Input channel: Channel 1
• PGA gain setting: x1
• Continuous conversion
Once the device is powered-up, the user can repro-
gram the configuration bits using I
2
C serial interface
any time. The configuration bits are stored in volatile
memory.
User selectable options are:
• Conversion bit resolution: 12, 14, 16, or 18 bits
• Input channel selection: CH1, CH2, CH3, or CH4.
• PGA Gain selection: x1, x2, x4, or x8
• Continuous or one-shot conversion
In the Continuous Conversion mode, the device
converts the inputs continuously. While in the One-Shot
Conversion mode, the device converts the input one
time and stays in the low-power standby mode until it
receives another command for a new conversion. Dur-
ing the standby mode, the device consumes less than
1 µA maximum.
4.2 Power-On-Reset (POR)
The device contains an internal Power-On-Reset
(POR) circuit that monitors power supply voltage (V
DD
)
during operation. This circuit ensures correct device
start-up at system power-up and power-down events.
The device resets all configuration register bits to
default settings as soon as the POR is set.
The POR has built-in hysteresis and a timer to give a
high degree of immunity to potential ripples and noises
on the power supply. A 0.1 µF decoupling capacitor
should be mounted as close as possible to the V
DD
pin
for additional transient immunity.
The threshold voltage is set at 2.2V with a tolerance of
approximately ±5%. If the supply voltage falls below
this threshold, the device will be held in a reset
condition. The typical hysteresis value is approximately
200 mV.
The POR circuit is shut-down during the low-power
standby mode. Once a power-up event has occurred,
the device requires additional delay time (approxi-
mately 300 µs) before a conversion takes place. During
this time, all internal analog circuitries are settled
before the first conversion occurs.
Figure 4-1 illustrates
the conditions for power-up and power-down events
under typical start-up conditions.
FIGURE 4-1: POR Operation.
4.3 Internal Voltage Reference
The device contains an on-board 2.048V voltage
reference. This reference voltage is for internal use
only and not directly measurable. The specification of
the reference voltage is part of the device’s gain and
drift specifications. Therefore, there is no separate
specification for the on-board reference.
4.4 Analog Input Channels
The user can select the input channel using the config-
uration register bits. Each channel can be used for
differential or single-ended input.
Each input channel has a switched capacitor input
structure. The internal sampling capacitor (3.2 pF for
PGA = 1) is charged and discharged to process a
conversion. The charging and discharging of the input
sampling capacitor creates dynamic input currents at
each input pin. The current is a function of the differen-
tial input voltages, and inversely proportional to the
internal sampling capacitance, sampling frequency,
and PGA setting.
V
DD
2.2V
2.0V
300 µS
Reset Start-up Normal Operation Reset
Time