EVB8740/EVB8741 Evaluation Board User Manual
SMSC EVB8740/EVB8741
7
Revision 1.0 (04-29-13)
USER MANUAL
External Clock
The EVB8740/EVB8741 can be configured to use an external clock by removing crystal Y1 and resistor
R20. A 25MHz +3.3V signal may then be applied to pin 1 of Y1 (which connects to pin 5 of the
LAN8740A/LAN8741A). Pin 2 of Y1 (which connects to pin 4 of the LAN8740A/LAN8741A) should be
left floating when using an external clock.
2.2.6
LEDs
Note:
LED1 and LED2 are located inside the RJ45 connector. LED1 and LED2 may function active-
high or active-low depending on the configuration of the REGOFF and nINTSEL straps,
respectively. Refer to the LAN8740A/LAN8741A Datasheet and LAN8740A/LAN8741A
schematics for additional information.
2.2.7
Test Points
Note 2.1
VDDCR is the in1.2V regulated output. When REGOFF is enabled, the internal
1.2V regulator is disabled. In this case, an external 1.2V regulator must be supplied to test
point TP3.
Note 2.2
The LAN8740A/LAN8741A’s VDDIO power may be supplied externally at a voltage other
than +3.3V as described in
Section 2.1, "Power," on page 3
Table 2.3 LEDs
REFERENCE
COLOR
INDICATION
LED1
Green
Link/Activity
Active when the PHY has established a valid link with a link partner
and blinks when activity is detected.
LED2
Yellow
Speed
Active when a 100BASE-TX link has been established. Inactive when
a 10BASE-T link has been established or during line isolation.
Table 2.4 Test Points
TEST POINT
DESCRIPTION
CONNECTION
TP1
+3.3V Test Point (Orange)
+3.3V
TP2
+5.0V Test Point (Red)
+5.0V
TP3
+1.2V VDDCR Test Point (Unpopulated)
+1.2V
TP4
Ground Test Point (Black)
Ground
TP5
VDDIO Test Point (Purple)
)
TP6
nPME Test Point (Unpopulated)
nPME (RXD2/nPME/RMIISEL)
TP7
AVDD Test Point (White)
AVDD
TP8
AVDD_ETH Test Point (Yellow)
AVDD_ETH
