EVB8740/EVB8741 Evaluation Board User Manual
Revision 1.0 (04-29-13)
6
SMSC EVB8740/EVB8741
USER MANUAL
2.2.3
nINT/TXER/TXD4 Pin Configuration (nINTSEL)
The nINT, TXER, and TXD4 functions share a common LAN8740A/LAN8741A pin. This pin can
operate in two functional modes: nINT (Interrupt) Mode and TXER/TXD4 Mode. TXER is also used in
EEE mode as TXER when TXEN = 1, and LPI when TXEN = 0. The nINTSEL configuration strap is
used to select one of these two modes. The EVB8740/EVB8741 must be properly configured for each
mode as follows:
nINT Mode
Depopulate R46.
Depopulate the 2-3 positions of JP3 and JP4.
Populate the 1-2 positions of JP3 and JP4 to pull-up the nINTSEL strap (nINT mode).
TXER/TXD4 Mode (Default EVB8740/EVB8741 Mode)
Depopulate the 1-2 positions of JP3 and JP4.
Populate the 2-3 positions of JP3 and JP4 to pull-down the nINTSEL strap (TXER/TXD4 mode).
Populate R46.
Note:
The nINTSEL configuration strap shares functionality with LED2. Therefore, LED2 may function
active-high or active-low depending on the nINTSEL configuration. For additional information
on the functionality of the nINT/TXER/TXD4 and LED2/nINTSEL pins, refer to the
LAN8740A/LAN8741A Datasheet and LAN8740A/LAN8741A schematics.
2.2.4
In1.2V Regulator Configuration (REGOFF)
The LAN8740A/LAN8741A provides the ability to disable the in1.2V regulator. When the
regulator is disabled, an ex1.2V must be supplied to the VDDCR pin (via TP3). Configuration
of the internal regulator is controlled by the REGOFF configuration strap. The EVB8740/EVB8741 must
be properly configured for each mode as follows:
In1.2V Regulator Enabled (Default EVB8740/EVB8741 Mode)
Depopulate the 2-3 positions of JP1 and JP2.
Populate the 1-2 positions of JP1 and JP2 to pull-down the REGOFF strap (enable regulator).
In1.2V Regulator Disabled
Depopulate the 1-2 positions of JP1 and JP2.
Populate the 2-3 positions of JP1 and JP2 to pull-up the REGOFF strap (disable regulator).
Note:
The REGOFF configuration strap shares functionality with LED1. Therefore, LED1 may
function active-high or active-low depending on the REGOFF configuration. For additional
information on the LED1/REGOFF pin and the disabling of the internal 1.2V regulator (power
sequencing requirements, etc.), refer to the LAN8740A/LAN8741A Datasheet and
LAN8740A/LAN8741A schematics.
2.2.5
Clock Configuration
The EVB8740/EVB8741 can be clocked via the onboard crystal oscillator or an optional external clock.
Crystal Oscillator (Default)
The 25 MHz crystal Y1 is connected to the internal oscillator of the LAN8740A/LAN8741A. A PLL
circuit in the LAN8740A/LAN8741A generates all the timing required by the PHY.
