Board Details
2015 Microchip Technology Inc.
DS50002427A-page 15
2.3
CLOCK
The LAN9252 requires a fixed-frequency 25 MHz clock source for use by the internal
clock oscillator and phase-locked loop (PLL). This is typically provided by attaching a
25 MHz crystal to the OSCI and OSCO pins.
10
GND
47
GND
86
NC
11
NC
48
GND
87
NC
12
NC
49
IRQ_MX-
_PIC24
88
NC
13
NC
50
NC
89
NC
14
NC
51
NC
90
NC
15
NC
52
NC
91
NC
16
NC
53
3V3
92
NC
17
SYNC1/LATC
H1
54
3V3
93
SQI_D0
18
SYNC0/LATC
H0
55
5V
94
NC
19
NC
56
5V
95
NC
20
NC
57
NC
96
NC
21
3V3
58
NC
97
WR/ENB
22
3V3
59
NC
98
RD/RD_WR
23
5V
60
D8
99
D14
24
5V
61
NC
100
D15
25
NC
62
D9
101
NC
26
NC
65
NC
102
SQI_CS0
27
NC
66
SQI_D2
103
CS
28
D11
67
SQI_D1
104
NC
29
NC
68
NC
105
D12
30
D10
69
NC
106
D13
31
NC
70
NC
107
3V3
32
NC
71
NC
108
3V3
33
A2
72
NC
109
D0
34
NC
73
SQI_SCK
110
D1
35
NC
74
SQI_D3
111
D2
36
IRQ_MZ
75
NC
112
D3
37
A4
76
NC
113
D4
38
NC
77
NC
114
D5
39
A3
78
NC
115
D6
40
NC
79
MZ_SDO
116
D7
41
GND
80
NC
117
NC
42
GND
81
NC
118
NC
43
NC
82
MZ_SCS
119
GND
44
NC
83
ALEHI_A1_J5 120
GND
45
NC
84
ALELO_A0_J
5
46
NC
85
NC
TABLE 2-1:
J1 CONNECTOR PIN DETAILS (CONTINUED)
Pin Number
Signal
Pin Number
Signal
Pin Number
Signal