Microchip Technology EVB-KSZ9563, User Manual

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EVB-KSZ9563 Evaluation Board User’s Guide
DS50002726A-page 16
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2018 Microchip Technology Inc.
Refer to the board schematics in Appendix B. “Schematics” and the KSZ9563 data
sheet for further details and usage on the GPIO signal pins.
2.5.5 INTRP_N Output
The INTRP_N output at test point TP14 provides the interrupt output from the KSZ9563
device. By default, it is active low and drives low to turn on D4 when asserted.
Refer to the board schematics in
Appendix B. “Schematics” and the KSZ9563 data
sheet for further details and usage on the INTRP_N signal.
2.5.6 PME_N Output
The PME_N output at test point TP16 provides the Power Management Event (PME)
interrupt output for Wake-on-LAN (WoL) from the KSZ9563 device. By default, it is
active low and drives low to turn on D5 when asserted.
Refer to the board schematics in
Appendix B. “Schematics” and the KSZ9563 data
sheet for further details and usage on the PME_N signal.
2.6 USING THE EVB-KSZ9563
The EVB-KSZ9563 plugs in directly to a mating Microchip host controller or processor
board, such as the SAMA5D3-ModuLAN Board, that delivers full power and provides
full register access and configuration via IBA, SPI, or I
2
C bus management.
Together, the EVB-KSZ9563 and the SAMA5D3-ModuLAN enable 10/100/1000-Mbps
Ethernet traffic switching across all three data ports of the KSZ9563 device, with RGMII
MAC port 3 connecting to the SAMA5D3 processor and PHY ports 1 and 2 connecting
via copper Ethernet cable (CAT-5 UTP or better) to external Ethernet devices.
All KSZ9563 registers are accessible via IBA, SPI, or I
2
C bus management from the
SAMA5D3-ModuLAN Board, enabling full evaluation and firmware development for all
KSZ9563 MAC/Switch features and interaction with upper network layers.
Refer to the SAMA5D3-ModuLAN Board documentation on its usage.
Figure 2-4 shows the EVB-KSZ9563 connected to the SAMA5D3-ModuLAN Board.
TABLE 2-3: GPIO SIGNAL HEADERS
Header Label Description Pin 1 Pin 2
J1 GPIO_2 The GPIO_2 pin is configurable to
implement IEEE1588 event trigger
outputs and timestamp capture inputs
to support real-time application
requirements. No Connect GPIO_2
(KSZ9563
pin 40)
J5 GPIO_1 The GPIO_1 pin is configurable to
implement IEEE1588 event trigger
outputs and timestamp capture inputs
to support real-time application
requirements. Ground GPIO_1
(KSZ9563
pin 39)