Microchip Technology EVB-KSZ8563, User Manual

Page: 22 / 32

EVB-KSZ8563 Evaluation
Board User’s Guide
DS500027
55A-page
2
2

2018 Microchip T
echnolo
gy Inc.
FIGURE B-1: EVB-KSZ8563 SCHEMATICS - KSZ8563 DEVICE, PIN STRAPPING, CLOCK, AND RESET
AVDDH
RX1_P
RX1_N
TX2_P
TX2_N
RX2_P
RX2_N
AVDDL
RX1_P 3
RX1_N 3
TX2_P 3
TX2_N 3
RX2_P 3
RX2_N 3
TX1_P
TX1_N
TX1_P 3
TX1_N 3
VDDIO
DVDDL
RX
D3_U1
RX
D2_U1
RX
D1_U1
RX
D0_U1
TX
D
3
TX
D
2
TX
D
1
TX
D
0
RX
_E
R_U1
RX
_DV
_
U1
RX
_CLK
_U1
SDI_SDA_MDIO
SDO
RESET_N
INTRP_N
PME_N
LED2_1
LED2_0
GPIO_2
GPIO_1
TX_ER
TX_EN
TX_CLK
SDI_SDA_MDIO 3
SDO 3
INTRP_N 3
PME_N 3
LED2_1 3
LED2_0 3
TX_ER 3
TX_EN 3
TX_CLK 3
TXD0 3
TXD1 3
TXD2 3
TXD3 3
RX_CLK 3
RXD0 3
RXD1 3
RXD2 3
RXD3 3
RX_ER 3
RX_DV 3
TXD0
TXD1
TXD2
TXD3
RXD0
RXD1
RXD2
RXD3
RX_DV
RX_CLK
RX_ER
SC
S
_
N
SC
L_
MD
C
IS
E
T
XI XO LE
D1
_0
LE
D1
_1
SCL_MDC 3
SCS_N 3
SCL_MDC
SCS_N
LED1_1 3
LED1_0 3
LED1_1
LED1_0
6.04k
1%
R49
External Reference Clocks
Input clock
Output clock MMCX_SYNCLKO
MMCX_XI
For AVB/1588
Place close to KSZ8563RNX
Close for MMCX
Open for test point
Open always
0.1uF DNP
C17
15pF
DNP
C14
XO
15pF
DNP
C13
XTAL-MEMS_XI
VDDIO
0.1uF
C12
Place close
to pin
RST_N input stability option
GPIO_2
GPIO_1
INTRP_N
PME_N
"INTRP_N"
"PME_N"
Br Grn
D4
Br Grn
D5
VDDIO
470R
R20
470R
R43
4.7k
R51
4.7k
R50
VDDIO
Strapping Pins
Refer to KSZ8563RNX Datasheet for detailed descriptions.
Strapping pins have internal pull-ups/pull-downs (default values);
external pull-ups/pull-downs are used to override internal values.
1
1000Mbps 0
Port_3 Speed in RGMII LED2_1
10/100Mbps (default)
0, 1
0, 0
1, 1
1, 0
RMII
MII (default)
Port_3 xMII Mode RXD3, RXD2
RGMII
<Reserved>
MII: PHY Mode
1
RMII: Clock Mode - RMII 50MHz
Reference Clock output on RX_CLK pin
0
Port_3 MII / RMII Configuration LED2_0
(default)
MII: MAC Mode
RMII: Normal Mode - RMII 50MHz
Reference Clock input to TX_CLK pin
1
Start Switch disabled
Switch will not forward packets until the Start bit is set in Register 0x0_3_00. 0
Start Switch Configuration LED1_0
Start Switch enabled (default)
Switch will forward packets immediately after reset.
Auto-Negotiation enable with EEE enable (default)
PHY Ports 1 and 2 Configuration RX_ER, PME_N
0, 0
0, 1
1, 1
1, 0
<Reserved>
Auto-Negotiation disable (Force 100Mbps, Full-duplex mode), and
Auto-MDIX disable (set to MDI-X mode)
Auto-Negotiation disable (Force 100Mbps, Full-duplex mode), and
Auto-MDIX disable (set to MDI mode)
VDDIO
RESET_N
0R
DNP
R18
0R
R19
0R
DNP
R48
0R
DNP
R47
25REFCLK_QTS
25REFCLK_QTS 3
from Samtec connector
22R R26
22R
R32
22R
R25
RX_DV_U1
RX_CLK_U1
RX_ER_U1
22R R21
22R R22
22R R23
22R
R24
RXD3_U1
RXD2_U1
RXD1_U1
RXD0_U1
RX_DV_U1
RX_CLK_U1
RX_ER_U1
RXD3_U1
RXD2_U1
RXD1_U1
RXD0_U1
i Net Class
ClassName: RGMII-RX_U1
100k
R12
VDDIO
MMBD914
D3
1uF
C8
1
4 2
3
SW1
Reset
0R
DNP
R13
0R
R11
RESET_N_QTS 3
RESET_N
from Samtec connector
RESET_N_QTS
RXD3_U1
RXD2_U1
RXD1_U1
RXD0_U1
RX_ER_U1
SDO_PU
4.7k R29
4.7k R36
4.7k
R39
4.7k
R42
4.7k DNP
R34
4.7k
R17
LED1_0
4.7k DNP R2
LED1_1_PU
LED2_0
LED2_1
PME_N
4.7k
R7
4.7k DNP
R35
4.7k DNP
R27
4.7k DNP R52
RXD3_U1
RXD2_U1
RXD1_U1
RXD0_U1
RX_ER_U1
SDO_PD
RX_DV_U1
LED1_0
LED1_1_PD
LED2_0
LED2_1
PME_N
750R DNP
R3
750R
R10
750R R33
750R R28
750R DNP
R38
750R
R44
750R DNP
R30
750R DNP
R31
750R DNP
R40
750R DNP R41
750R R37
750R R16
1, x
0, 1
0, 0
Management Mode RXD1, RXD0
I2C Slave
MDC/MDIO (default)
SPI Slave
1
0
IBA Mode LED1_1
Disable
Enable (default)
1
0
Quiet-WIRE SDO
Enable
Disable (default)
0R
DNP
R14
0R R15
TP14
TP16
*2-3
Quiet-WIRE
1
2
3
J1
LED1_1_PD
LED1_1_PU
LED1_1
1
2
3
J5
SDO_PD
SDO_PU
SDO
*2-3
IBA Mode
GPIO_2
GPIO_1
XI
SYNCLKO
SYNCLKO
GND
Test Options
Rosc
Rxtal
Rxo
P/N = ABM8G-25.000MHZ-B4Y-T (Murata)
P/N = DSC1001CI2-25.0000 (Microchip)
For XTAL:
Populate Rxtal and Rxo
DNP Rosc
For OSC (default):
Populate Rosc
DNP Rxtal and Rxo
DNP
1
MMCX, Vert
J4
DNP
1
MMCX, Vert
J3
JP2
JP1
TX_ER
TX_EN
TX_CLK
TXD0
TXD1
TXD2
TXD3
i Net Class
ClassName: RGMII-TX
4.7k
DNP
R53
VDDIO
VDD
4
GND
2
STBY#
1
OUT
3
Y1
TX1P
2
TX1M
3
RX1P
5
AVDDL
4
RX1M
6
AVDDH
8
TX2P
9
TX2M
10
AVDDL
11
RX2P
12
RX2M
13
AVDDL
14
AV
D
D
H
15
DVDD
L
17
RXD3
18
RXD2
19
RXD1
20
RXD0
21
RX_CL
K
/
REFCLK
O
22
VDDIO
23
RX_DV
/
CRS_DV
/
RX_CTL
24
RX_ER
25
TXD3
26
TXD2
27
TXD1
28
TXD0
29
TX_CLK / REFCLKI
30
DVDDL
31
TX_EN / TX_CTL
32
TX_ER
33
DVDDL
34
VDDIO
36
GPIO_1
40
GPIO_2
41
DVDDL
42
LED2_0
43
LED2_1
44
PME_N
45
INTRP_N
46
RESET_N
47
SDO
48
SDI / SDA / MDIO
49
SC
S
_
N
52
KSZ8563RNX
Paddle Ground (Chip Bottom)
(QFN64)
SCL
/
MDC
53
P_GND
65
DV
D
D
L
54
L
ED1_0
55
L
ED1_1
56
VD
D
IO
57
DV
D
D
L
59
AV
D
D
L
60
XO
61
XI
62
GND
58
ISET
64
AVDDH
1
AVDDL
7
GND
16
GND
35
GND
37
GND
39
VDDIO
38
GND
50
VDDIO
51
GND
63
U1