Micro Crystal
Ultra Small Real-Time Clock Module with SPI-Bus Interface
RV-8063-C7
October 2018
11/58
Rev. 1.1
CONTROL REGISTERS
3.2.
To ensure that all control registers will be set to their default values, the V
DD
level must be at zero volts at initial
power-up. If this is not possible, a reset must be initiated with the software reset command when power is stable.
Refer to section SOFTWARE RESET for details.
00h - Control1
Control and status register 1.
Address
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h
Control1
TEST
SR
STOP
SR
CIE
12_24
CAP
Reset
0
0
0
0
0
0
0
0
Bit
Symbol
Value
Description
7
TEST
0
Normal mode.
1
External clock test mode. Do not use.
6
SR
Software Reset (see SOFTWARE RESET)
0
No software reset.
1
Initiate software reset; this bit always returns a 0 when read. For a software
reset, 01011000 (58h) must be sent to register Control1.
5
STOP
STOP bit (see STOP BIT FUNCTION)
0
RTC clock runs.
1
RTC clock is stopped; the upper part of the RTC divider chain flip-flops
(prescaler F2 to F14) are asynchronously set logic 0. The CLKOUT
frequencies 32.768 kHz, 16.384 kHz and 8.192 kHz are still available.
4:3
SR
Software Reset (see SOFTWARE RESET)
00
No software reset.
11
Initiate software reset; this bits always returns a 0 when read. For a
software reset, 01011000 (58h) must be sent to register Control1.
2
CIE
Compensation Interrupt Enable (see FREQUENCY OFFSET COMPENSATION)
0
No compensation interrupt will be generated.
1
Compensation interrupt pulses will be generated on pin
INT
̅̅̅̅̅
at every
compensation cycle.
1
12_24
12 or 24 hour mode (see TIME AND DATE REGISTERS and ALARM REGISTERS)
0
24 hour mode is selected (0 to 23).
1
12 hour mode is selected (1 to 12).
0
CAP
0
Must always be written with logic 0.
