Hardware/Software Interface
Page 65
4.2
FPGA IP Core Implementation
The UART, CAN and GPIO interfaces of the Box PC are controlled using IP cores in an
FPGA. See the following table for a list of the IP cores.
Table 32.
Chameleon table
Name
Device Variant Revision
Interrupt Group Instance BAR Offset Size
16Z125_UART
125
0
11
6
0
4
0
220
8
16Z125_UART
125
0
11
4
0
0
0
3F8
8
16Z125_UART
125
0
11
3
0
1
0
2F8
8
16Z125_UART
125
0
11
7
0
2
0
3E8
8
16Z125_UART
125
0
11
5
0
3
0
2E8
8
16Z082_IMPULSE
82
0
2
3F
0
0
1
800
20
16Z034_GPIO
34
0
A
B
0
0
1
E200
20
16Z034_GPIO
34
0
A
B
0
2
1
E240
20
16Z037_GPIO
37
1
1
B
0
0
1
E260
20
16Z126_FLASH
126
0
6
3F
0
0
1
E280
20
16Z029_CAN
29
1
12
B
0
0
1
E400
100
16Z076_QSPI
76
0
7
B
0
0
1
E800
800
16Z029_CAN
29
1
12
B
0
1
1
F000
100
