AT3550 User Guide V1.00
February 11, 2005
page 11 of 16
4. OPERATION
4.1 ACTIVE REMAP™ AND WRITE LIMITATIONS
Unlike mechanical drives, wherein the wear-out mechanism results from starting
and stopping the platters and the rotation of the spindle motors, the wear-out
mechanism for any solid state flash drive resides in writing to the non-volatile
memory, which in Memtech's case is NAND E
2
PROM. Writing the to the memory
devices requires that electrons be first removed from, and then trapped on the
floating gate in each cell using Fowler-Nordheim tunneling techniques. This
process is inherently harsh on the oxide layer isolating the floating gate from the
silicon substrate in the device, and establishes the write cycle endurance of each
cell in a device as specified by the device manufacturer.
To overcome this limitation, Memtech Solid State Flash Drives have been
designed with Active Remap™, which, on a detected cell failure, moves the
entire failing block to a reserved location and maps the failing block out of
active memory. This process is automatic and invisible to the user. It
extends the device's useful life almost 100 fold, and makes the Memtech
series of Solid State Drives suitable for both read mostly and read/write
applications.
In an ongoing effort to determine the durability of the flash components and
in turn extend the life of our products, Memtech has also conducted several
endurance tests using our flash drives. The results were very
encouraging. During testing, done under both benign and harsh operating
conditions, Memtech observed and documented an erase/write cycle
endurance of 8 to 30 million cycles. This is compared to the flash
manufacturer's test and report of only 100,000 to 250,000 erase/write
cycles for the flash devices.
Reading the NAND E
2
PROM has no adverse effects on the storage cells or
oxide layers, and is therefore unlimited.
4.2 ECC
The NRZ data interface used by the IDE controller implements a CRC/ECC
mechanism to detect and correct any errors in the data stored in the flash. This
polynomial is capable of correcting three 8-bit data bursts in a single sector, and
detecting up to six 8-bit error bursts per sector.
An extensive retry algorithm is implemented on the AT3550, so that single event
disturbances such as ESD can be readily overcome. Probability of miscorrection
is approximately 10
-20
per bit corrected for a 512-byte field.
