MEDIATEK MT6252, Design Manual

Page: 92 / 166

This section states the layout recommendations for the Image Sensor
Design Notice Design Notice – – Dual Camera Dual Camera
●
PCB Layout Design Notice (2/3)
(high priority-Must!!)
This section states the layout recommendations for the Image Sensor
clock signals. Refer to below figure for the clock topology and below table for
the routing guidelines. Each clock shall be routed surround with ground plan.
The R
d
is optional that could be different from 0 or 22 Ω if the different
controller I/O is designed or the different driving strength is assigned.
Parameter Routing Guideline
Reference plane Route microstrip over unbroken ground plane. p p g p
Main trace patterns (MCLK
PCLK)
W = 4-mil, S ≥ 4-mil.Surround the CLK with ground plan.
Break-out/Break-in area (under
the BGA package area)
W ≥ 3-mil, S ≥ 3-mil.
Damping resistor (R
d
) Optional, 0 or 22 Ω (Near the Image Sensor).
Max. TL0 + TL1 (BB ball to Main
Image Sensor Connect)
4,500 mils
Max. TL1 (Branch points to Sub
1 500 mils
Image Sensor Connect)
1,500 mils
Length matching for Data-to-
PCLK(TL0+TL1)
(PCLK length − 500-mil) ≤ DQ length ≤
(PCLK 500-mil)
R k
Each clock shall be routed surround with ground plan (high priority)
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Remark
g g y
[MCLK, PCLK]