MEDIATEK MT6252 Design Manual Download Page 12

Page: 12 / 166

MT6252 Chip configuration design notice (

SRCLKENAI

))

1. Please remember

to enable internal Pull down

when this pin is used as 26MHz clock

request from 6252 (In general this is used by BT)

request from 6252. (In general , this is used by BT)

2011/1/17

Summary of Contents for MT6252

Page 3: ...cker Charger Linear charger Pulse charger 1 Pulse charger 2 Important SW setting 3 Nokia Charger support A di Cl D AB A Cl AB A 1 2 i 1 li ti Audio Class D AB Amp Class AB Amp 1 2 in 1 application 2 Important part placement Speech SW algorithm Same with 53 1 Important part placement Camera 2M VGA 1 Reference design LCM 2 8V IO LCM 1 8V IO LCM 1 1 8V IO LCM MSDC 4 bit IO 1 bit IO 1 IOT 2 DAT3 as Ca...

Page 4: ...ement notice TXM PRF88144B Rx SAWs 26MHz crystal must close to BB MT6252 SOC C load Must close 32 768KHz Serial Flash 32 768KHz crystal must close to BB must close to BB 2008 06 Copyright MediaTek Inc All rights reserved 3 ...

Page 5: ...n J6 should be connected to ground J6 should be connected to ground 2 2 PMU_TESTMODE PMU_TESTMODE Pin Pin H5 should be connected to ground H5 should be connected to ground 3 3 VMSEL VMSEL Pin J3 should be connected to ground Pin J3 should be connected to ground 2011 1 17 Copyright MediaTek Inc All rights reserved 4 ...

Page 6: ...round on PWM PWM if PWM is if PWM is used used 2 You can connect 2 You can connect PWM PWM to ground directly if PWM is not used But please to ground directly if PWM is not used But please 2011 1 17 Copyright MediaTek Inc All rights reserved 5 g y p g y p must configure this as GPIO input mode and pull up should not be enabled must configure this as GPIO input mode and pull up should not be enable...

Page 7: ...nnect DAIRST and DAISYNC DAIRST and DAISYNC to VIO directly if these 2 pin are to VIO directly if these 2 pin are t d f th f ti B t l t fi thi GPIO t d f th f ti B t l t fi thi GPIO 2011 1 17 Copyright MediaTek Inc All rights reserved 6 not used for any other function But please must configure this as GPIO not used for any other function But please must configure this as GPIO input mode and pull d...

Page 8: ...ce BB 1V8 1V8 1 1 VM_SEL VM_SEL connected to ground connected to ground Î Î VM 1 8V VM 1 8V MT6252 only support 1 8V memory VMSEL should always be low MT6252 only support 1 8V memory VMSEL should always be low y pp y y y pp y y 2011 1 17 Copyright MediaTek Inc All rights reserved 7 ...

Page 9: ...ip configuration design notice BB MT6252 Chip configuration design notice BB 1 1 FSOURCE FSOURCE should be connected to ground should be connected to ground 2011 1 17 Copyright MediaTek Inc All rights reserved 8 ...

Page 10: ...hould be pulled to VIO by 47Kohm memory card socket side should be pulled to VIO by 47Kohm memory card socket side should be pulled to VIO by 47Kohm memory card socket side should be pulled to VIO by 47Kohm 2 You also can enable internal pull up but reserving SMT space for external pull 2 You also can enable internal pull up but reserving SMT space for external pull up resistors is recommended up ...

Page 11: ...capacitors capacitors Power of SIM comes from 6302 Power of SIM comes from 6302 1 Please remember to add bypass capacitors on VSIM1 and VSIM2 even 1 Please remember to add bypass capacitors on VSIM1 and VSIM2 even th 2 LDO t d i th 2 LDO t d i 4 SIM li ti 4 SIM li ti 2011 1 17 Copyright MediaTek Inc All rights reserved 10 these 2 LDOs are not used in these 2 LDOs are not used in 4 SIM application ...

Page 12: ...ll down to enable internal Pull down when this pin is used as 26MHz clock when this pin is used as 26MHz clock request from 6252 In general this is used by BT request from 6252 In general this is used by BT request from 6252 In general this is used by BT request from 6252 In general this is used by BT 2011 1 17 Copyright MediaTek Inc All rights reserved 11 ...

Page 14: ...Hz Serial Flash 78MHz 104MHz Clock Rate 104MHz 52MHz PSRAM 104MHz EMI voltage 1 8V 1 8V 1 8V 1 MT6252 support 78MHz and 104MHz QPI mode Serial Flash 1 MT6252 support 78MHz and 104MHz QPI mode Serial Flash 2 The power domain 2 The power domain of Serial flash is same as internal stacked of Serial flash is same as internal stacked PSRAM So PSRAM So please use please use 1 8V serial flash instead of ...

Page 15: ...must be 1 8V must be 1 8V Please connect the pins according to following table Please connect the pins according to following table 6252 Serial flash SHOLD DQ3 SSWP DQ2 SIN DQ1 SOUT DQ0 SCS Chip enable SCK CLK Interface 2011 1 17 Copyright MediaTek Inc All rights reserved 14 SCK CLK EN25S64 U1006 EN25S64 64M 1 8v EON Contact Bull Tang bull1975 gmail com 13502888931 ...

Page 16: ...6252 Memory Layout design notice MT6252 MT6252 Serial Flash Serial Flash Memory should be placed as close to MT6252 as possible Memory should be placed as close to MT6252 as possible 2011 1 17 Copyright MediaTek Inc All rights reserved 15 ...

Page 17: ...ended that these 2 packages should be reserved on your PCB It s recommended that these 2 packages should be reserved on your PCB Their pins are fully compatible but pin locations are slightly shifted Their pins are fully compatible but pin locations are slightly shifted Please overlap the pins for SMT compatible Please overlap the pins for SMT compatible 2011 1 17 Copyright MediaTek Inc All rights...

Page 18: ...emory Layout design notice The traces of memory should not be crossed by other traces or power The traces of memory should not be crossed by other traces or power Nice to have Nice to have 2011 1 17 Copyright MediaTek Inc All rights reserved 17 ...

Page 19: ... 6 5 6 5 p p Serial Flash Serial Flash There should be a ground plane beneath the Serial Flash and QPI traces of There should be a ground plane beneath the Serial Flash and QPI traces of MT6252 Ni t h MT6252 Ni t h 2011 1 17 Copyright MediaTek Inc All rights reserved 18 MT6252 Nice to have MT6252 Nice to have ...

Page 21: ...Content MT6252 Introduction MT6252 Introduction General description Block diagram Block diagram LDO list Comparison Comparison Function Description Reference design Appendix ppe d Copyright MediaTek Inc All rights reserved 20 ...

Page 22: ...t IC Highly integrated functions fulfill all power requirement in handset system system LDO Analog LDO 4 Digital LDO 9 Digital LDO 9 Audio Amplifier Class AB 0 7W 3 7V 1 Charger controller Charger controller AC USB Pulse Charger Driver Driver Parallel LCM backlight LED 4 Keypad back light 1 Copyright MediaTek Inc All rights reserved 21 ...

Page 24: ...2 8 100 1uF Far end bypass cap VTCXO 2 8 40 1uF Far end bypass cap VCAMD 1 3 1 5 1 8 2 5 2 8 3 0 3 3 100 1uF Far end bypass cap VIO 2 8 200 2 2uF Far end bypass cap VIO 2 8 200 2 2uF SS 40uS VUSB 3 3 50 1uF Far end bypass cap VSIM 1 8 3 0 30 1uF Far end bypass cap 1 3 1 5 1 8 2 5 VSIM2 1 3 1 5 1 8 2 5 2 8 3 0 3 3 30 1uF Far end bypass cap VIBR 1 3 1 5 1 8 2 5 2 8 3 0 3 3 150 1uF Far end bypass cap...

Page 25: ...tent Content Content Content MT6252 Introduction MT6252 Introduction Comparison Function Description Power on timing Driver Reference design Appendix Appendix Copyright MediaTek Inc All rights reserved 24 ...

Page 26: ...able control Note 1 Luminance become lower when low battery Please follow Criteria Vth Vf 0 25V to avoid this issue E Ex Set VBAT low voltage shutdown at 3 5V Select LED Vf 3 5 0 25 3 25V will keep luminance equal under l ti normal operation range Note 2 PWM should set higher to prevent LCM from flickering in l VBAT PWM f 20kH i d d t low VBAT PWM frequency 20kHz is recommended to prevent both LCM...

Page 27: ...klight Current sink for backlight When ISINK control by When ISINK control by PWM dimming PWM dimming by PWM3 by PWM3 When ISINK control by When ISINK control by Register mode It could be Register mode It could be controlled independently controlled independently Copyright MediaTek Inc All rights reserved 26 p y p y ...

Page 28: ...0 PMIC_ISINKX_CON0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name RG ISINKX STEP RG_ISIN KX MO RG_ISI NKX E _ _ _ DE _ N Type RW RW RW Reset 0 0 0 RG_ISINK0_STEP 6 4 000 001 010 011 100 101 110 111 ISINK0 current mA 4 8 12 16 20 24 RG_ISINKX_STEP Coarse 6 step current level for ISINK 000 4mA 101 24mA 4mA per step ISINK0 current mA 4 8 12 16 20 24 RG_ISINKX_MODE ISINKX PWM MODE SEL 1 Register contr...

Page 30: ... RG_KP LED_M ODE RG_ KPLE D_EN Type RW RW RW RW RW Reset 0 0 0 0 0 RG_KPLED_SEL 3 bits for KPLED current adjustment RG_KPLED_SEL 2 0 000 001 010 011 100 101 110 111 8 steps in total The minimal current should be no less than 60mA at 111 step KPLED current 1X 2X 3X 4X 5X 6X 7X 8X RG KPLED MODE KPLED enable mode select RG_KPLED_MODE KPLED enable mode select 0 pwm mode controlled by hardware PWM1 out...

Page 31: ...Content Content Content Content MT6252 Introduction MT6252 Introduction Comparison Function Description Reference design Schematic Appendix pp Copyright MediaTek Inc All rights reserved 30 ...

Page 32: ...EY and BAT_ON Please reserve 1k resistor on phone PCB to protect PWRKEY no matter if Please reserve 1k resistor on phone PCB to protect PWRKEY no matter if PWRKEY connect to any I O connector or not Please reserve 1k resistor on phone PCB to protect BAT ON phone PCB to protect BAT_ON pin if BAT_ON is used to detect battery Copyright MediaTek Inc All rights reserved 31 ...

Page 33: ...1V 500mW to protect the IC against low frequency voltage surge Put it between battery connector and MT6252 Notice If using IO connector or test point to supply VBAT for download manufacture or repair should let VBAT trace passing zener diode and 22uF capacitor before entering IC Notice Using 5 1V zener will introduce some leakage when VBAT 4 2V Notice Using 5 1V zener will introduce some leakage w...

Page 34: ...n 200mW and can sink more exceptional surge voltage current MT6252 must selcet 5 1V 500mW zener to enhance MT6252 must selcet 5 1V 500mW zener to enhance VBAT pin protection Ir 100uA Vr 4 2V Ta 25 C Using 5 1V zener will introduce some leakage when VBAT 4 2V Large Ir introduce some leakage when VBAT 4 2V Large Ir current will introduce more leakage current Copyright MediaTek Inc All rights reserve...

Page 35: ...0mW SOD123 9 Tony Kao 886 2 23761153 886 987 265 997 886 987 265 997 Email tony kao onsemi com 2 JIANGSU CHANGJIANG 长电科技 MMSZ5231B 500mW SOD123 72 Mr Chan 0510 86858061 13601525970 E mail cyz cj elec com E mail cyz cj elec com 3 Prisemi PZ3D4V2H 500mW SOD323 11 5 Mobile 13502888931 Email bull1975 gmail com 4 Prisemi PZ5D4V2H 500mW SOD523 4 85 5 Vishay MMSZ4689 V 500mW SOD123 7 Mike_Wang 886 911313...

Page 36: ...ilter VBAT Input Filter VBAT Input Filter VBAT Input Filter All bypass cap should be as close to MT6252 IC as possible Recommend reserve 0 ohm between VBAT pin VBAT_RF VBAT_ANALOG for analog LDO quality analog LDO quality Copyright MediaTek Inc All rights reserved 35 ...

Page 37: ...rence design Reference design Schematic Schematic Bypass Capacitor Bypass Capacitor At least 1 cap larger than 1uF on power trace VRF VCAMA VIO larger than 2uF Copyright MediaTek Inc All rights reserved 36 ...

Page 38: ...erence design Reference design Schematic Schematic Bypass Capacitor for AVDD and VDD Bypass Capacitor for AVDD and VDD Reserve 0 ohm resistor for audio quality Copyright MediaTek Inc All rights reserved 37 ...

Page 40: ...pport battery type Li ion Li ion Li ion Support battery type Li ion Li ion Li ion VCHG OVP 7V 7V 10 5V Default off CV 4 2V 4 2V 4 2V comparator CC 160mV R 160mV R 160mV R Pre_ charge 24mV R 20mV R 20mV R Battery OVP 4 3V 4 3V 4 35V Watchdog timer Yes Yes Yes Pre charge safety timer NO NO 50 minutes Passed element P MOSFET SD P MOSFET SD BJT N MOSFET Pre charge CC overlap Yes No Yes Copyright Media...

Page 41: ...unt regulator for charger block Current passed HV Isolation MOSFET 1 D203 NC 1 2 C C C E C B U200 1 3 2 2 1L1B SMD PNM723T703E0 2 3 1 VDRV U200 Power rating 30V GATDRV Control pin Component HV Isolation MOSFET U204 Power rating 30V R211 VA ISENSE 4mil 40mil Current sense Resistor I_CHR R213 24K 0 2 J201 BC 4565 M 03 01 LF VBAT 1 BAT_TYPE 2 GND 3 R215 1K VBAT AUX_IN4 1 4mil 40mil V MLV200 TVS200 A ...

Page 42: ... TSOP6 100 NC 3A peter liu st com 02 23762971 2 On semi NSS35200MR6 T1G 1 TSOP6 100 400 2A Tony Kao tony kao onsemi com 886 2 23761153 T1G 886 2 23761153 886 987 265 997 3 NXP PBSS5350D 0 7 SC 74 SOT 200 NC 3A Mag Cheng mag cheng nxp com 3 NXP PBSS5350D 0 7 SC 74 SOT 457 200 NC 3A mag cheng nxp com 886 987 49186 886 2 8170 9076 Direct SOT23 4 Presemi PT236T30E2 1 2 SOT23 6L TSOP6 100 NC 3A bull197...

Page 43: ...arge current 0 72C for Li ion 900mAHr M di i ti f t l BJT 1W D t 8 8 1 Max power dissipation of external BJT 1W Duty 8 8 1 Vchg 3 3 0 65 0 88 1 Î Vchg 5 04V I 0 65A Vchg 3 3 0 425 0 88 1 Î Vchg 6 0V I 0 425A g g Vchg 3 3 0 20 0 88 1 Î Vchg 9 0V I 0 20A Any charging time VCHG VBAT 0 2 Î VCHG 4 4 V VCHG V 5 10 5 04 6 0 9 0 V IBAT 200 425 650 5 mA 4 4 200 425 650 mA ...

Page 44: ...imum input voltage up to 30V Support low cost linear and Nokia adaptor charger 9 3V Meet 2010 China charger standard 12V OVP CC d t t l CC mode current control Constant current pre charging Charger OVP and battery OVP Pre charge CC safety timer Watchdog timer Copyright MediaTek Inc All rights reserved 43 ...

Page 45: ...rent Setting Sense Resistor 0 2 Ohm 0 2 Ohm 0 1 Ohm 0 2 Ohm 0 2 Ohm Pre Charge 62 5 100 200 50 100 Pre Charge 62 5 100 200 50 100 0 62 5 62 5 125 50 100 1 90 90 180 87 5 200 CC 2 150 150 300 150 400 3 225 225 450 225 425 4 300 300 600 300 550 5 450 450 900 450 650 6 650 X X 650 700 6 650 X X 650 700 7 800 X X 800 800 Copyright MediaTek Inc All rights reserved 44 ...

Page 46: ...eter c bmt_customized_struct bmt_custom_chr_def xxxxxxxxxxxxx KAL FALSE enable checking temperature while charging KAL_FALSE enable checking temperature while charging KAL TRUE enable checking charging voltage while charging KAL_TRUE enable checking charging voltage while charging This should be TRUE This should be TRUE Copyright MediaTek Inc All rights reserved 45 This should be TRUE This should ...

Page 47: ...ge will reach 9 3V For HV input adaptor must care charger OVP and BJT power p p g p dissipation Configure charger OVP for Nokia Charger Step 1 SW OVP 9 Modify Chr_parameter c 6500000 10500000 VCHARGER_HIGH Step 2 HW OVP 9 Please contact MTK to modify HW OVP for SW patch default is 7V BJT power dissipation BJT Power Dissipation and Charge Current page 2011 1 17 Copyright MediaTek Inc All rights res...

Page 48: ...r supply source and it s a 2 8V CHR_LDO Charger power supply source and it s a 2 8V shunt regulator VDRV Charge passed element control pin VDRV Charge passed element control pin BATSNS Battery voltage sense pin ISENSE C t i ISENSE Current sense pin BATON Battery detection pin If this pin is large than 2 5V ill di bl h i 2 5V will disable charging Copyright MediaTek Inc All rights reserved 47 ...

Page 49: ...ection threshold voltage is 4 3V at Charger detect the detection threshold voltage is 4 3V at charge off state Charger over voltage g g protection HW default is disable SW can customize VCH G disable SW can customize Default is 7 5V MT6252 MT6252 Copyright MediaTek Inc All rights reserved 48 ...

Page 50: ...Charger Detection Charger Detection Charger Detection Charger Detection VCDT HV VTH valid if VCDT HV EN 1 _ _ _ _ CHRDET CHRDET VCDT_LV_VTH always valid Copyright MediaTek Inc All rights reserved 49 ...

Page 51: ...T_HV_VTH Min Typical Max 09 5 7 6 6 3 10 6 175 6 5 6 825 11 6 65 7 7 35 12 7 125 7 5 7 785 12 7 125 7 5 7 785 13 8 075 8 5 8 93 14 9 025 9 5 9 97 15 9 975 10 5 11 02 Other adding below circuitry to increase a OVP path BATON toggle threshold is 2 5V D202 1 1 BAT_Temp VCHG R230 BAT54CXV3T1 1 2 2 3 3 VCHG_1_Diode BATON R231 5 1K 1 2 R230 6 8K 1 2 2 Copyright MediaTek Inc All rights reserved 50 ...

Page 52: ...aturation If Q1 does not go into saturation I1 β1xI2 Assume I1 450mA β1 200 I2 2 25mA If Q1 goes into saturation look up the h t i ti t bl t t th characteristic table to get the relationship between I1 and I2 Build in 256 steps CSDAC for current p driving control Copyright MediaTek Inc All rights reserved 51 ...

Page 53: ...SDEC Charge current β1 I_CSDEC I CSDEC i 14 8 A I_CSDEC maximum 14 8mA I_CSDEC selection 1 LSB 55uA Current step 55uA 200 β1 11mA DC Current Gain β must be 100 300 at Ic 0 5A Copyright MediaTek Inc All rights reserved 52 ...

Page 54: ...e 6 times 30mins time out PMU CV 4 2V 2level 1 VBAT is full Precharge state Charge complete state Pause State V_PROTECT_HIGH_LI Vbat off Vbat_off 3 8V or in stand by Vbat_off 4 11V V FULL2FAST THR Vbat_off 4 05V and in talking mode 4 05V and in talking mode Post Full Wait 90secs Vbat_off 4 05V and in talking Fast CC PMU CV 4 2V 1 detected rate 6 times _ 4 05V and in talking mode or in stand by mod...

Page 55: ... No charge state Precharge state 100mA Charger plug in CC mode state 450 A Charger plug in Charging time 2hr 5min 450mA Top off mode Fast CC Full state 1hr 32min Re Charging state TOP off mode 4 1V Pe Full state Top off mode Fast CC Mode 25min Full state Pe Full state Vb t 4 1V Vb t 4 2V 8min Vbat 4 1V Vbat 4 2V ...

Page 56: ... duty to detect charger plug out Otherwise has reverse current and can t detect charger plug out BJT DC Current Gain will effect current step and accurate accurate Smaller DC Current Gain get more accurate Too small DC Current Gain to charge up zero voltage battery Vbat 1V CSDEC will limit at 4 step 0 23mA Copyright MediaTek Inc All rights reserved 55 ...

Page 57: ...sipation must be For thermal dissipation concern the U200 power dissipation must be large than 1W VCE Collector Emitter Voltage 30V Ic 0 8A Depend on application Ic 0 8A Depend on application U204 N MOS PNM723T703E0 2 V th h ld 1 5V Id 0 1 A Vgs threshold 1 5V Id 0 1mA VDS 30V Depend on application RDS ON 10 ohm ID 10 mA VGS 2 5 V C200 VCHG input cap If want to support VCHG up to 30V please change...

Page 58: ...d pad of the U200 Current passed component should connect to a large copper ground plane to get good thermal performance performance ISENSE and BATSNS should be connected as the below figure The trace from Rsense to battery connector should not share with The trace from Rsense to battery connector should not share with other VBAT traces ISENSE BATSNS should be routed as differential traces which a...

Page 61: ...22 8 22 8 16 8 dB gain step size 2dB 2dB 2dB Engineer mode range 0 255 0 255 0 255 audio buffer gain range dB 22 23 22 23 22 17 dB gain step size 3dB 3dB 3dB Engineer mode range 0 255 0 255 0 255 Engineer mode range 0 255 0 255 0 255 SPK AMP Amp Type ClassAB D ClassD ClassAB gain range dB 0 21 Class AB 6 27 Class D 12 18dB 0 22 5dB gain step size 3dB x 1 5dB Copyright MediaTek Inc All rights reser...

Page 62: ...3 9 A di Si l h ti d l t The signal of Audio block should shielding by GND Audio Signal schematic and layout C218 GND net should connect to C3 AGND28_AFE pad first then direct through Via to Main GND Copyright MediaTek Inc All rights reserved 61 ...

Page 63: ...udio 4 9 Audio Power schematic and layout C225 GND side should connect to AGND28_AFE first then short to main GND and close to ball C9 Audio Power schematic and layout VA C225 C 1000 nF 0402 2 1 Copyright MediaTek Inc All rights reserved 62 ...

Page 64: ... 100p C41 100n 10u R66 1 5K MICP1 2 MICN1 2 XMIC R59 1K near BB located in Shielding case R69 1K 33p 33p ADC_USB 2 HOOK DETECTION R65 1 5K C48 100p L5 BLM15BB750SN1 C44 100n MK1 Microphone 1 2 C45 10u MICP0 2 Shielding case C63 100p R71 100 C53 47u MP3_OUTL 2 near BB located in Shielding case XMP3_L HEADSET EarPhone L6 BLM15BB750SN1 C50 100n R68 1 5K U50 _ESD C51 33p U51 _ESD C52 33p MICN0 2 C56 4...

Page 65: ...ck pin 3 5 connection to R317 to GND Step 2 Plug in earphone Audio Jack pin 3 5 dis connected EINT 1 pull high C63 100p R71 100 C53 47u MP3_OUTL 2 XMP3_L HEADSET EarPhone C56 47u C64 33p R72 100 C65 33p MP3_OUTR 2 XMP3_R p R73 1K p EINT_HEADSET 2 connect EINT to MP3 OUT for cost effective solution connect EINT to MP3_OUT for cost effective solution connect to L channel to avoid POP noise when use ...

Page 66: ...lug out to High plug in kal_bool aux_state LEVEL_LOW void AUX_EINT_HISR void ilm_struct aux_ilm if aux_state LEVEL_HIGH ifdef AUX_DEBUG dbg_print Interrupt Plugout n r endif Example for EINT status if from High plug out to Low plug in kal bool aux state LEVEL HIGH kal_bool aux_state LEVEL_HIGH void AUX_EINT_HISR void ilm_struct aux_ilm if aux_state LEVEL_LOW ifdef AUX_DEBUG dbg_print Interrupt Plu...

Page 67: ...W THD N 10 VDD 3 3V RL 8Ω 650mW THD N 1 VDD 4 2V RL 8Ω 850mW THD N 1 VDD 4 2V RL 8Ω 850mW THD N 1 VDD 3 6V RL 8Ω 500mW Although MT6252 class AB power output is 0 85W at 8 Ω because congenital power source limitation is 4 2V from VBAT but compare with other discrete amplifiers MT6252 equal but compare with other discrete amplifiers MT6252 equal other amplifier in performance Copyright MediaTek Inc ...

Page 68: ...LS2 C61 100p L8 BLM18PG221SH1 LOUD SPEAKER V M1005C080MTAAB L10 BLM18PG221SH1 C54 33p C55 33p REC V M1005C080MTAAB L8 BLM18PG221SH1 SPKP0 2 SPKN0 2 Vendor P N Rdc ohm Rate current mA BLM18PG221SH1 0 1 1400 BLM15PD800SN1 0 07 1500 BLM18KG221SN1 0 05 2200 T5 M T4 M Murata BLM18KG221SN1 0 05 2200 BLM18KG331SN1 0 08 1700 BLM18SG221TN1 0 04 2500 BLM18SG331TN1 0 07 1500 BLM18EG221SN1 0 05 2000 TDK MPZ16...

Page 69: ...m between VB_OP VB_ON to limit the voltage level at VB_OP VB_ON Class AB Amp Class D external amp 2 analog switches should be put between VB OP ON and R1 Note1 put between VB_OP ON and LSPK_OP ON Note1 The R1 Ron of the analog switch should equal to Analog switch R1 Note1 g q 12ohm Class D Amp 2011 1 17 Copyright MediaTek Inc All rights reserved 68 ...

Page 71: ...11 should be put as close as possible 2 L303 L305 C310 C316 C317 T305 and T306 should be l h i h R302 1K R303 1 5K L303 routed in differential 1 2 close to the microphone 3 GND of C316 and C317 should be connected together and then to the GND MICN0 1 MICP0 1 C310 100p C312 100n C301 100n C311 10u MIC301 Microphone 1 2 T305 BLM15BB750SN1 L305 BLM15BB750SN1 then to the GND 4 GND of T305 and T306 sho...

Page 72: ...hould be put close to BB 2 The GND of C333 and C334 MICBIASP Should be routed should connect together and then connect to the GND MICN1 1 R310 1K C327 C326 100n Headset GND Should be routed in differential 1 4 3 The GND of C327 and headset should connect together and then to the main MICP1 1 MIC_HP 9 C333 C328 100p C334 R311 1 5K C332 100n 10u 1 3 g GND by single via 4 C327 should be put close to ...

Page 73: ...ing Example Placement and routing Example AU_OUT0_P N _ _ MP3_OUTL R AU_MIC_BIAS MICP0 N0 MICP1 N1 MICP0 N0 1 AU_VCM cap should be as close as to the BB chip G f C 2 The GND of AU_VCM should be connected to pin C3 first and then connect to the main GND by single via by single via ...

Page 74: ...th other traces The GND of AU VCM cap should be connected to the The GND of AU_VCM cap should be connected to the ball C3 first and then connected system GND with single via to make sure the GND is clear g For 6 layers PCB the system GND is the GND plan of the PCB For 4 layers PCB the system GND is the GND that has largest GND area top or bottom la er GND area top or bottom layer The via should be...

Page 75: ...pplication circuit 1 application circuit 2 resistor 12Ω are used to 2 resistor 12Ω are used to construct the equivalent 32Ω load at HS 32Ω load at HS A resistor 32Ω is needed to avoid the current to avoid the current leakage from SPK amp output to the HS voice p buffer ...

Page 77: ...Image Sensor Interface Parallel Image Sensor Interface BB Chip Pin definition Camera side CMVREF VSYNC CMHREF HSYNC CMPCLK PCLK CMMCLK MCLK SDA SIOD SDA SIOD SCL SIOC CMRST RESETB CMRST RESETB CMPDN PWDN CMDAT0 CMDAT7 DATA0 DATA7 76 Copyright MediaTek Inc All rights reserved ...

Page 78: ...e Sensor Interface Serial Image Sensor Interface BB Chip Pin definition Camera side MCLK Master Clock CSD SPI Data Output CSK SPI Clock Output SDA I2C Data Output SDA I2C Data Output SCL I2C Clock Output CAMRST Reset CMPDN PWDN 77 Copyright MediaTek Inc All rights reserved ...

Page 81: ...e Circuit Please check VCAMD Current can meet sensor requirement or not For Parallel Sensor EMI filter cap VCAMD Imax 100mA max loading is 30pf For Serial sensor EMI filter cap max loading is 30pf Copyright MediaTek Inc All rights reserved 80 ...

Page 82: ...ut 2 Clock Group Trace Clock Group Trace Power Trace Power Trace Clock Group Trace Clock Group Trace Layout 3 Layout 3 Camera Digital Power Camera Digital Power Trace Trace Layout 4 Layout 4 Data Group Trace Data Group Trace Layout 5 Layout 5 Control Group Control Group Trace Trace p p Trace Trace Copyright MediaTek Inc All rights reserved 81 ...

Page 83: ...e do not place the PCB Component Placement recommend interference do not place the sensor module near or beneath the antenna The sensor module s power supplies inductors beads resistors capacitors should be resistors capacitors should be placed as close as possible to the connect Copyright MediaTek Inc All rights reserved 82 ...

Page 84: ...and impedance changes When it becomes necessary to turn 90 use two 45 turns or an arc instead of making a single 90 turn This reduces reflections on the signal by minimizing impedance discontinuities impedance discontinuities Do not route signal traces under crystals oscillators clock synthesizers magnetic devices Route all traces over continuous planes Keep all signals clear of the core logic set...

Page 85: ...placed as close as camera connector as camera connector 2 Don t routing the trace to cross EMIF input and output L1 L2 3 Reduce the routing trace on top layer 4 Don t routing the unrelated signal on L2 pad GND signal is OK GND signal is OK Copyright MediaTek Inc All rights reserved 84 ...

Page 86: ...or the length matching Data DQ 0 7 CMVREF CMHREF Image sensor data 0 7 input Image sensor vertical reference signal input Image sensor horizontal reference signal input g g p Clock MCLK PCLK Image sensor master clock output Image sensor pixel clock input PCLK Image sensor pixel clock input SCL SDA I2C clock output I2C data input output Control CMRST CMPDN CMFLASH p p Image sensor reset signal outp...

Page 87: ...all be routed surround with g g g p ground plan Parameter Routing Guideline Reference plane Route microstrip over unbroken ground or power plane Main trace patterns Image Sensor Data W 4 mil S 4 mil Break out Break in area under the BGA package area W 3 mil S 3 mil Max TL0 BB ball to Image Sensor Connect 4 800 mils Length matching Max Trace length 500mil Trace length Max Trace length Copyright Med...

Page 88: ... controller I O is designed or the different driving strength is assigned Parameter Routing Guideline Reference plane Route microstrip over unbroken ground plane Main trace patterns MCLK PCLK W 4 mil S 4 mil Surround the CLK with ground plan PCLK Break out Break in area under the BGA package area W 3 mil S 3 mil Damping resistor Rd Optional 0 or 22 Ω Near the Image Sensor Max TL0 TL1 4 500 mils Le...

Page 89: ...or the routing guidelines g g Parameter Routing Guideline Reference plane Route microstrip over unbroken ground or power plane Reference plane Route microstrip over unbroken ground or power plane Main trace patterns W 4 mil S 4 mil Break out Break in area under the W 3 mil S 3 mil BGA package area W 3 mil S 3 mil Max TL0 6000 mils Remark Control Group shall be routed surround with ground plan Copy...

Page 90: ...ed for the length matching Data DQ 0 7 CMVREF CMHREF Image sensor data 0 7 input Image sensor vertical reference signal input Image sensor horizontal reference signal input g g p Clock MCLK PCLK Image sensor master clock output Image sensor pixel clock input PCLK Image sensor pixel clock input SCL SDA I2C clock output I2C data input output Control CMRST CMPDN CMFLASH p p Image sensor reset signal ...

Page 91: ...und plan P t R ti G id li Parameter Routing Guideline Reference plane Route microstrip over unbroken ground or power plane Main trace patterns Image Sensor Data W 4 mil S 4 mil Break out Break in area under the BGA package area W 3 mil S 3 mil Max TL0 TL1 BB ball to Main Image Sensor Connect 4 800 mils Max TL1 Branch points to Sub Image Sensor Connect 1 500 mils Length matching TL0 TL1 Max Trace l...

Page 92: ...fferent driving strength is assigned Parameter Routing Guideline Reference plane Route microstrip over unbroken ground plane p p g p Main trace patterns MCLK PCLK W 4 mil S 4 mil Surround the CLK with ground plan Break out Break in area under the BGA package area W 3 mil S 3 mil Damping resistor Rd Optional 0 or 22 Ω Near the Image Sensor Max TL0 TL1 BB ball to Main Image Sensor Connect 4 500 mils...

Page 93: ...er Routing Guideline Reference plane Route microstrip over unbroken ground or power plane Main trace patterns W 4 mil S 4 mil Main trace patterns W 4 mil S 4 mil Break out Break in area under the BGA package area W 3 mil S 3 mil Max TL0 TL1 BB ball to Main Image Sensor Connect 6 000 mils Max TL1 Branch points to Sub Image Sensor Connect 2 000 mils Remark Control Group shall be routed surround with...

Page 94: ...erconnecting Serial Image Sensor Interface Group Signal Name Description lengths in the controller package should be calculated for the length matching SPI CSD CSK Image sensor SPI data output Image sensor SPI CLK output Clock MCLK Image sensor master clock output SCL I2C clock output Control SDA CMRST p I2C data input output Image sensor reset signal output Copyright MediaTek Inc All rights reser...

Page 95: ...uidelines Data group shall be routed surround with ground plan Parameter Routing Guideline Reference plane Route microstrip over unbroken ground or power plane Main trace patterns Image Sensor Data W 4 mil S 4 mil Break out Break in area under the BGA package area W 3 mil S 3 mil Max TL0 BB ball to Image Sensor Connect 6 000 mils Length matching in PCB 100 mils Copyright MediaTek Inc All rights re...

Page 96: ...nal that could be different from 0 or 22 Ω if the different controller I O is designed or the different driving strength is assigned Parameter Routing Guideline Reference plane Route microstrip over unbroken ground plane p p g p Main trace patterns MCLK PCLK W 4 mil S 4 mil Surround the CLK with ground plan Break out Break in area under the BGA package area W 3 mil S 3 mil the BGA package area Dam...

Page 97: ...ing guidelines for the routing guidelines Parameter Routing Guideline Reference plane Route microstrip over unbroken ground or power plane Reference plane Route microstrip over unbroken ground or power plane Main trace patterns W 4 mil S 4 mil Break out Break in area under the W 3 mil S 3 mil BGA package area W 3 mil S 3 mil Max TL0 6000 mils Remark Control Group shall be routed surround with grou...

Page 98: ...the routing guidelines Analog Power shall be routed surround with ground plan Parameter Routing Guideline Reference plane Route microstrip over unbroken ground or power plane Main trace patterns Analog Power W 12 mil S 4 mil with GND trace Remark Analog power must be routed surround with ground plan De couple cap shall connect to main ground directly Copyright MediaTek Inc All rights reserved 97 ...

Page 99: ... Digital Power shall be routed surround with ground plan P t R ti G id li Parameter Routing Guideline Reference plane Route microstrip over unbroken ground or power plane Main trace patterns Digital Power W 12 mil S 4 mil with GND trace Remark Digital power shall be routed surround with ground plan De couple cap shall connect to main ground directly Must Copyright MediaTek Inc All rights reserved ...

Page 102: ...n 1 Reserve external PU resistors for DAT1 2 3 MCINS in connector side 2 Reserve ESD protection device on CMD CLK DAT MCINS with Cap 15pF 3 VIO must always be on for hot plug detection VIO VIO VIO VIO MCDA0 MCCM0 MCCLK MCINS V TVS01 V TVS4 V TVS2 V TVS3 2011 1 17 101 ...

Page 103: ... PU resistors for DAT1 2 in connector side 2 Reserve ESD protection device on CMD CLK DAT MCINS with Cap 15pF 3 DAT3 must be PD with external 470Kohm resistor 4 Compile option for DAT3 detection MSDC TFLASH DAT3 1BIT HOT PLUG 4 Compile option for DAT3 detection __MSDC_TFLASH_DAT3_1BIT_HOT_PLUG__ 5 VIO must always be on for hot plug detection VIO MCDA0 MCCM0 MCCLK MCINS VIO VIO V TVS01 V TVS4 V TVS...

Page 104: ...43 2 2 TF Card VMC 10u 10V Y5V C715 U212 SHDN 3 VIN 1 100n 16V X7R C716 VMC External LDO SD_POWEN DA0 CM0 MCDA3 MCDA2 CLK NC R 47K ohm 0402 1 MCDA3 MCDA2 R1644 NC R 47K ohm 0402 1 J301 DAT2 1 CD DAT3 2 CMD 3 VDD 4 CLK 5 VSS2 6 DAT0 7 DET_A 9 DET_B 10 GND1 11 GND2 12 VMC_Socket MCDA0 MCCLK MCCM0 GND 2 BP 4 VOUT 5 nc C717 10u 10V Y5V C721 200mA output MCD C40 C 1000 nF 0402 2 1 MCC MCDA1 MCC V TVS01...

Page 105: ...5pF VIO R1642 NC R 47K ohm 0402 1 2 MCDA1 R1643 1 2 MCDA3 R1644 2 J301 TF Card VIO MCDA0 MCCM0 MCDA3 MCDA2 MCDA1 MCCLK NC R 47K ohm 0402 MCDA3 MCDA2 NC R 47K ohm 0402 1 J301 DAT2 1 CD DAT3 2 CMD 3 VDD 4 CLK 5 VSS2 6 DAT0 7 DAT1 8 DET_A 9 DET_B 10 GND1 11 GND2 12 VMC_Socket MCDA0 MCCLK MCCM0 M C40 C 1000 nF 0402 2 1 M M V TVS01 V TVS2 V TVS3 T Flash12 DAT1 2011 1 17 104 ...

Page 106: ...Layout Guidelines Layout Guidelines y y 1 DAT CMD CLK 一起走 2 若無法全部一起走優先順序為 DAT CLK CMD 3 CLK 左右要包GND 避免受到干擾 4 DAT CMD CLK 線長最大誤差控制在1000mil以內預估time difference在 160pS以內 2011 1 17 105 ...

Page 108: ...splay Interface S t CPU 8 9 16 bit i t f Supports CPU 8 9 16 bit interface Dedicated HW tearing free control Power Power Support 1 8v IO level LCM 6252 only support 1 8V I O Support Parallel 4 LCM backlight controller Dual display feature is supported Parallel 8 9 main Parallel 8 9 sub Parallel 8 9 main SPI sub 2011 1 17 Copyright MediaTek Inc All rights reserved 107 ...

Page 109: ...D19 17 D18 18 19 LCM Data All LCM data pin are reserved at BB side For 8 bit interface some LCM use lower byte D 7 0 some D 23 16 B d t i t t th t LCM D17 19 D16 20 D15 21 D14 22 D13 23 D12 24 D11 25 D10 26 D9 27 D8 28 D7 29 NLD7 NLD8 use D 23 16 Be sure data pin connect to the correct LCM pins Backlight Connect backlight anode to VBAT with a bypass cap LED K1 LED_A Backlight D7 D6 30 D5 31 D4 32 ...

Page 110: ...AA13 RD LRSTB AC5 RESET NLD8 NLD0 W20 AA21 Y21 AB22 W18 Y20 AA17 Y17 AA14 D17 19 D16 20 D15 21 D14 22 D13 23 D12 24 D11 25 D10 26 D9 27 D8 28 D7 29 NLD7 NLD8 NLD8 NLD0 Y20 AA17 Y17 AA14 Note1 NLD15 NLD9 AB23 V21 T19 Y10 Y9 AA10 AA9 LED K1 LED_A Backlight D7 D6 30 D5 31 D4 32 D3 33 D2 34 D1 35 D0 36 LEDA 37 LEDK1 38 39 NLD4 NLD5 NLD1 NLD2 NLD3 NLD0 NLD7 NLD6 1 LPTE AC4 FMARK F_Sync BLC BLC_EN LED_K...

Page 111: ...B LCD_TE pin AC4 MT6252 Pin definition LCM side LSDA EA4 AA17 SDI J1 VIO VM 1uF 2 1 1uF 2 1 LSDA EA4 AA17 SDI LSDI EA6 Y20 SDO LSCK EA3 AA14 SCK VCI 1 IOVCC 2 GND 3 LEDA 4 LEDK1 5 6 2 LED_A 1 LED_K1 LRSTB AC5 RESET LSCE0B Y19 SCS LCD TE AC4 FMARK LSCK LEDK2 6 SDI 7 SDO 8 SCS 9 SCK 10 RESET 11 12 LRSTB LPTE 1uF 2 LED_K2 LSDI LSDA LSCE0B LCD_TE AC4 F_Sync LCM 12 FMARK_Fsync LPTE 2011 1 17 Copyright ...

Page 112: ...Dual LCM Dual LCM LCM Design Note LCM Design Note Dual LCM Dual LCM Dual LCM mode Parallel LCM 1 LPCE0B Parallel LCM LPCE0B Parallel LCM 2 6252 LPCE1B Serial LCM 6252 LSCE0B LCM 2011 1 17 Copyright MediaTek Inc All rights reserved 111 ...

Page 113: ...CM 要求的FPC pin数量尽量少会做成仅支援 2 8V的方式 2 WistronOPT 90 新開發產品全面支援2 8v 1 8v兼容目前的产品都尽可能将IO Power Supply单独接口但是由于个别客 3 BYD TBD 目前的产品都尽可能将IO Power Supply单独接口但是由于个别客户早期的主板只保留了1个2 8V Power Supply的供应 LCD产品不得不将IOVCC与VCI连接在一起使用这种单电源供应产品不是很多大部分集中在小尺寸产品上目前我司LCM是有一些在接口上只有一路电压即2 8V 当然这些产品应用的手机平台不全部是MTK的对于这个问题我司后 4 BOE 81 些产品应用的手机平台不全部是MTK的对于这个问题我司后续与客户进行项目沟通时会传递这个信息尽量在新项目中采用分开电压的设计 5 Tainma SH 90 绝大部分...

Page 114: ...dule Spec This LCM has only One Power Pins no separated VCI and IOVCC power pins Supply voltage allows 3V only which means IO level can t support 1 8V VDD typical 3V Non separate power pin p p Only one pin Separate p power pin 2011 1 17 Copyright MediaTek Inc All rights reserved 113 ...

Page 115: ...vel Trend MTK recommend LCM connection Data bus B b d Data bus B b d LCD Driver Baseband VIO 2 8V LCD Driver Baseband VIO 2 8V VMEM 1 8V LCD Driver LCD Driver VCI IOVCC 2 8V VCI 2 8V IOVCC 1 8V 2011 1 17 Copyright MediaTek Inc All rights reserved 114 ...

Page 117: ... Outline Outline Outline Reference design Reference design META tools Key RF components Modify BPI and timing for MT6252 Modify BPI and timing for MT6252 2008 06 Copyright MediaTek Inc All rights reserved 116 ...

Page 119: ...Quad Quad band Schematic band Schematic Quad Quad band Schematic band Schematic MT6252 RF part R SAW Rx SAWs TXM RF7170 X TAL X TAL 2008 06 Copyright MediaTek Inc All rights reserved 118 ...

Page 121: ... LOG file RST file INI file input file CAL file Barcode 6 4 Barcode 2 Calibration items AFC RX path loss TX PCL 3 PA t d PCL 2 3 PA type and PCL Select PA type in the scroll bar 4 Other settings Select GMSK and or EPSK 5 3 mode AFC type is Crystal 5 Select instrument Select CMU or 8960 De select Reset CMU200 5 De select Reset CMU200 6 Start calibration 2008 06 Copyright MediaTek Inc All rights res...

Page 122: ...le INI file input file CAL file Barcode 4 Barcode 2 Calibration items AFC RX path loss TX PCL 3 PA t 7 2 3 PA type Select PA type in the scroll bar 4 Other settings Select GMSK and or EPSK 5 3 mode AFC type is Crystal 5 Select instrument Select CMU or 8960 De select Reset CMU200 5 De select Reset CMU200 6 Select FHC 7 Start calibration 6 2008 06 Copyright MediaTek Inc All rights reserved 121 ...

Page 123: ... File and Initial Files Calibration File and Initial Files Calibration file traditional calibration MT6252 CFG Initial file traditional calibration MT6252 ini 2008 06 Copyright MediaTek Inc All rights reserved 122 ...

Page 125: ...ss Harmonics attenuation Isolation System performance under normal and extreme condition RMS and peak phase error Frequency error ORFS Switching transient Sensitivity Spurious emission p FEM Front End Module ASM with RX SAW Characteristics Insertion loss Attenuation Isolation System Performance Under normal and extreme conditions System Performance Under normal and extreme conditions RMS and peak ...

Page 126: ...B Diplexer RX Diplexer RX PCS DCS EGSM GSM850 HB LB Diplexer RX SAW Diplexer RX SAW Please turn on SWAP function for diplexer MT6252 RX TX PCS DCS EGSM GSM850 HB LB function for diplexer SAW usage PCB Layout Sketch MT6252 2008 06 Copyright MediaTek Inc All rights reserved 125 PCB Layout Sketch ...

Page 127: ...ujitsu FAR G5KM 942M50 Y4NY FAR G6KM 1G9600 Y4NZ 850 900 1800 1900 1 in 4 out 1 8x1 4 MT6253 SAMSUNG SFWM81DY102 SFWG42MY002 850 900 1800 1900 1 in 4 out 1 8x1 4 MT6253 EPCOS No products checking develop 850 900 1 i 4 t 1 8 1 4 MT6253 EPCOS No products checking develop schedule with engineers 850 900 1800 1900 1 in 4 out 1 8x1 4 MT6253 Hitachi Media No products checking develop schedule with engin...

Page 128: ...omponents Qualified for MT6253 Type Vendor Part Number Size mm2 Band Supported Tx Module RFMD RF7170 6 63 x 5 24 Semi Quad N t Th t t i th RF t l t h ld b th 6253 b t thi Note The target is these RF external components should be the same as 6253 but this qualify schedule is TBD 2008 06 Copyright MediaTek Inc All rights reserved 127 ...

Page 129: ...s Qualified Crystal Components Vendor Part Number Freq MHz CL pF Size mm2 Status TXC 7M26000028 26 7 5 3 2 x 2 5 Approved Note Don t use MT6139 MT6140 s AD6548 Crystal for MT6252 Note The target is these RF external components should be the same as 6253 but this qualify schedule is TBD 2008 06 Copyright MediaTek Inc All rights reserved 128 ...

Page 135: ...race TOP L1 VIA TYPE TOP layer RF trace Microstrip line Ref GND plane L2 TOP L1 L2 RF trace L2 L2 RF trace strip line Ref GND plane L1 or L3 control line Power line L3 Bottom layer RF trace BOTTOM L4 Microstrip line Ref GND plane L3 2008 06 Copyright MediaTek Inc All rights reserved 134 ...

Page 137: ...Crystal MT62 2 Crystal and its trace directly refer to global ground keep out L1 L2 ground global GND 3 Crystal ground pin directly connect to global ground do not connect to other layer GND global GND L1 L2 L3 2008 06 Copyright MediaTek Inc All rights reserved 136 ...

Page 138: ...GND H22 is directly connected to global ground 5 PIN FREF J22 should be shielded in inner layer and its via y should keep far away from Pin XTAL G23 and trace 2008 06 Copyright MediaTek Inc All rights reserved 137 ...

Page 141: ...he same between the differential pair b GND keep at least larger than 4 time of differential pair distance r 4xd d r 9 Avoid GND split under MT6252 especially for L2 9 Avoid GND split under MT6252 especially for L2 L1 L2 L3 L4 2008 06 Copyright MediaTek Inc All rights reserved 140 ...

Page 142: ...e as close as possible to MT6252 11 GND of AVDD28_RF1 C17 AVDD28_RF2 E21 E22 decoupling cap is directly connected to global ground 12 Place AVDD28_TCXO H20 bypass cap as close as possible to MT6252 possible to MT6252 2008 06 Copyright MediaTek Inc All rights reserved 141 ...

Page 143: ...or Camera LCM and MSDC the clock and data should have better GND protection Avoid power trace or other trace routing parallel with clock and data other trace routing parallel with clock and data 15 Place memory as close as possible to MT6252 2008 06 Copyright MediaTek Inc All rights reserved 142 ...

Page 145: ...1 custom rf h file L1_custom_rf h file PA control logic and schematic of RF module Due the BPI amount of MT6252 is less than MT6253 it is necessary to modify Vlogic pin to BPI_BUS 1 Defunded function of BPI 2011 1 17 Copyright MediaTek Inc All rights reserved 144 ...

Page 146: ...y band Standby mode CW1 SX N divider Warm up mode CW133 Enter TX mode TX mode CW2 mode 000 TRX 10 TX sleep mode y Idle PT1 245 Qb Dummy Idle PT2 20 Qb Dummy TRSW Band SW PA EN PT2B 0 Qb TX mode Idle PT3 31 Qb Return to idle TX EN 40 30 BSI CLK 26MHz Send CW2 first in ST0 TX TX TX FS 0 ST2 ST1 ST0 0 ST3 0 52 BSI 270 325 36 PT2B BPI PT2 PT1 PT3 0 BPI 20 245 31 APC APCDACCON APCCON APCMID APCOFF 36 1...

Page 147: ... RX CW2 Set TRX band Nfrc mode 010 CW57 Set AFC value Standby mode CW1 SX N divider Warm up mode CW96 RX gain TX mode CW2 mode 000 TRX 10 TX sleep mode Idle PR1 40 Qb Dummy PR2 33 Qb Dummy Idle PR3 6 Qb Return to idle TRSW Band SW PA EN RX EN 36 0 TX TX RX FS 0 SR2 SR1 SR0 0 SR3 0 71 BSI 148 213 0 BPI PR2 PR1 PR3 BPI 33 40 6 2011 1 17 Copyright MediaTek Inc All rights reserved 146 ...

Page 151: ...ample for GSM PR1 Example for GSM_PR1 Example for GSM_PR1 PR1 0 0 0 0 0 0 Idle 0 0 0 0 0 0 0 0 0000 0000 0000 Binary Transform Hexadecimal 000 PDATA_GSM_PR1 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 150 ...

Page 152: ...ample for GSM PR2 Example for GSM_PR2 Example for GSM_PR2 PR2 0 TRSW Band SW 0 1 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0010 Binary Transform Hexadecimal 2 PDATA_GSM_PR2 0x2 2011 1 17 Copyright MediaTek Inc All rights reserved 151 ...

Page 153: ... for GSM PR3 Example for GSM_PR3 Example for GSM_PR3 PR3 0 Return to Idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 Binary Transform Hexadecimal 000 PDATA_GSM_PR3 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 152 ...

Page 154: ...ample for GSM PT1 Example for GSM_PT1 Example for GSM_PT1 PT1 0 0 0 0 0 0 Idle 0 0 0 0 0 0 0 0 0000 0000 0000 Binary Transform Hexadecimal 000 PDATA_GSM_PT1 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 153 ...

Page 155: ...ample for GSM PT2 Example for GSM_PT2 Example for GSM_PT2 PT2 0 0 0 0 0 0 Idle 0 0 0 0 0 0 0 0 0000 0000 0000 Binary Transform Hexadecimal 000 PDATA_GSM_PT2 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 154 ...

Page 156: ...M PT2B Example for GSM_PT2B Example for GSM_PT2B PT2B 0 TRSW PAEN on BANDSW_DCS 0 1 0 0 1 PAEN on 1 0 0 0 0 0 0 0 0000 0001 0010 Binary Transform Hexadecimal 12 PDATA_GSM_PT2B 0x12 2011 1 17 Copyright MediaTek Inc All rights reserved 155 ...

Page 157: ... for GSM PT3 Example for GSM_PT3 Example for GSM_PT3 0 PT3 0 0 0 0 0 Return to Idle 0 0 0 0 0 0 0 0 0000 0000 0000 Binary Transform Hexadecimal 000 PDATA_GSM_PT3 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 156 ...

Page 158: ...ample for DCS PR1 Example for DCS_PR1 Example for DCS_PR1 PR1 0 0 0 0 0 0 Idle 0 0 0 0 0 0 0 0 0000 0000 0000 Binary Transform Hexadecimal 000 PDATA_DCS_PR1 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 157 ...

Page 159: ...ample for DCS PR2 Example for DCS_PR2 Example for DCS_PR2 1 PR2 1 1 0 0 0 TRSW Band SW 0 0 0 0 0 0 0 0 0000 0000 0011 Binary Transform Hexadecimal 3 PDATA_DCS_PR2 0x3 2011 1 17 Copyright MediaTek Inc All rights reserved 158 ...

Page 160: ... for DCS PR3 Example for DCS_PR3 Example for DCS_PR3 PR3 0 Return to Idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 Binary Transform Hexadecimal 000 PDATA_DCS_PR3 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 159 ...

Page 161: ...ample for DCS PT1 Example for DCS_PT1 Example for DCS_PT1 PT1 0 0 0 0 0 0 Idle 0 0 0 0 0 0 0 0 0010 0000 0000 Binary Transform Hexadecimal 000 PDATA_DCS_PT1 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 160 ...

Page 162: ...ample for DCS PT2 Example for DCS_PT2 Example for DCS_PT2 PT2 0 0 0 0 0 0 Idle 0 0 0 0 0 0 0 0 0000 0000 0000 Binary Transform Hexadecimal 000 PDATA_DCS_PT2 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 161 ...

Page 163: ...S PT2B Example for DCS_PT2B Example for DCS_PT2B PT2B 1 TRSW PAEN on BANDSW_DCS 1 1 0 0 1 PAEN on 1 0 0 0 0 0 0 0 0000 0001 0011 Binary Transform Hexadecimal 13 PDATA_DCS_PT2B 0x13 2011 1 17 Copyright MediaTek Inc All rights reserved 162 ...

Page 164: ... for DCS PT3 Example for DCS_PT3 Example for DCS_PT3 PT3 0 Return to Idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 Binary Transform Hexadecimal 000 PDATA_DCS_PT3 PDATA_IDLE 2011 1 17 Copyright MediaTek Inc All rights reserved 163 ...

Page 165: ...difference between APC off and PT3 is 26QB The difference between APC off and PT3 is 26QB Due the transceiver architecture deference SR timing have to be modified BPI BPI is expressed by hexadecimal but edited by binary 2011 1 17 Copyright MediaTek Inc All rights reserved 164 ...

Search results

Summary of Contents for MT6252

Reviews:

MEDIATEK MT6252, Design Manual, Page: 12 / 166

Search results

Summary of Contents for MT6252

Reviews: