Measurement Computing PCIM-DAS1602/16, User Manual

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6 REGISTER ARCHITECTURE
6.1 OVERVIEW
PCIM-DAS1602/16 operation registers are mapped into I/O space. Unlike ISA bus designs, this
board has several base address regions, each corresponding to a reserved block of addresses in
I/O space. Of the six Base Address Regions (BADRs) available per the PCI 2.1 specification,
five are implemented in this design and are summarized in Table 6-1 as follows.
Table 6-1. PCIM-DAS1602/16 BADR Mapping
8-bit Byte 82C55 Digital I/O registers BADR4
8-bit Byte Pacer, Counter, Trigger, Interrupt, and
Digital I/O configuration registers BADR3
16-bit Word ADC and DAC data registers BADR2
32-bit Double Word PCI I/O mapped configuration registers BADR1
32-bit Double Word PCI memory mapped configuration registers BADR0
Operations Function I/O Region
BADRn will likely be different on different machines. Assigned by the PCI BIOS, these Base Address
values cannot be guaranteed to be the same even on subsequent power-on cycles of the same machine.
All software must interrogate BADR0 at run-time with a READ_CONFIGURATION_DWORD
instruction to determine the BADRn values.
BADR0 and BADR1 are used for PCI configuration. Only the PCI Interrupt Control/Status Register
(BADR1 + 4Ch) should be used. All others should not be written to. This Board uses the PLX PCI9052
PCI Bus Interface chip. For additional information on BADR0 and BADR1, refer to the data sheet.
NOTE: All unused bits are denoted by an X. They are 0 for a read operation and don’t cares for a write
operation.
6.2 BARD1 REGISTER
INTERRUPT CONTROL INTERRUPT STATUS BADR1 + 4Ch
WRITE FUNCTION READ FUNCTION REGISTER
BADR1+4Ch
READ/WRITE
LINTE 1 INT 0 0 0 PCINTE 0
0 1 2 3 4 5 6 31:7
This register controls the interrupt features of the PLX-9052. For proper operation, the predefined bits,
bit 1 = 1 and bits 3, 4, 5, 7 to 31 = 0, must not be changed.
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