PCI-DAS1602/16 User's Guide
Specifications
25
Counter
*Note: Pins 21, 24, and 25 are pulled to logic high via 10K resistors.
Table 11. Counter specifications
Counter type
82C54
Configuration
Two 82C54 chips containing three 16-bit down counters each
82C54A:
Counter 0 — ADC residual sample
counter.
Source:
ADC Clock.
Gate:
Programmable source.
Output:
End-of-Acquisition interrupt.
Counter 1 — ADC pacer lower
divider
Source:
10 MHz oscillator
Gate:
Tied to Counter 2 gate, programmable source.
Output:
Chained to Counter 2 Clock.
Counter 2 — ADC pacer upper
divider
Source:
Counter 1 Output.
Gate:
Tied to Counter 1 gate, programmable source.
Output:
ADC Pacer clock (if software selected), available at user
connector.
82C54B:
Counter 0 — pretrigger mode
Source:
ADC Clock.
Gate:
External trigger
Output:
End-of-Acquisition interrupt.
Counter 0 — non-pretrigger mode:
user counter 4
Source:
User input at 100pin connector or internal 10MHz (software
selectable)
Gate:
User input at 100pin connector.
Output:
Available at 100pin connector.
Counter 1 — DAC pacer lower
divider
Source:
10 MHz oscillator
Gate:
Tied to Counter 2 gate, programmable source.
Output:
Chained to Counter 2 Clock.
Counter 2 — DAC pacer upper
divider
Source:
Counter 1 Output.
Gate:
Tied to Counter 1 gate, programmable source.
Output:
DAC Pacer clock, available at user connector.
Clock input frequency
10 MHz max
High pulse width (clock input)
30 ns min
Low pulse width (clock input)
50 ns min
Gate width high
50 ns min
Gate width low
50 ns min
Input high
2.0 volts min, 5.5 volts absolute max
Input low
0.8 volts max, -0.5 volts absolute min
Output high
3.0 volts min @ -2.5 mA
Output low
0.4 volts max @ 2.5 mA
Crystal oscillator frequency
10 MHz
Frequency accuracy
50 ppm
Power consumption
Table 12. Power consumption specifications
+5 V operating (A/D converting to FIFO)
2 A typical, 2.1 A max
