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In summary form, the registers and their function are listed in the following table.

Table 4-2. Register Map

None

D/A Most Significant Nibble and
Channel address 

BASE + 1

None

D/A Least Significant Byte

BASE + 0

READ FUNCTION

WRITE FUNCTION

ADDRESS

These two registers control all of the DACs on the CIO-DAC##-I. The first register,
BASE + 0, contains the least significant eight bits of D/A code and is written first.

BASE + 0

D12

(LSB)

D11

D10

D9

D8

D7

D6

D5

0

1

2

3

4

5

6

7

The second register contains the most significant four bits of D/A code and the four
bits that determine which channel the data will be sent to.  This register is written to
second.  A write to this register updates the output of the selected D/A with all 12
bits of the D/A code contained in the two registers.  

BASE + 1

D4

D3

D2

D1

(MSB)

CH0

CH1

CH2

CH3

0

1

2

3

4

5

6

7

D12: 1  Data bits

CH3:0  Channel value (0000 = channel 0, 0101 = channel 5, etc.)

Updating the output of a particular DAC channel is a matter of calculating the code
for the output value desired and combining it with the channel number.

To calculate the data code, you first select the output you desire, then apply a
transfer function to that value.  The transfer function for code = output is:

FSI / 4095 * CODE = Current Out +4 mA or   CODE = Current Out - 4 / 16 *  4095

Full scale current (FSI) is not 20 mA, it is 20 - 4 or  16 mA. Use this in the equation
above.

For Example:

If CODE = 0, current output  = 4 mA
If CODE = 4095, current output  = 20 mA

8

Summary of Contents for CIO-DAC08-I

Page 1: ...CIO DAC08 I and CIO DAC16 I User s Manual Revision 3 October 2000...

Page 2: ...lt from its use No license is granted by implication or otherwise under any patent or copyrights of Measurement Computing Corporation All rights reserved No part of this publication may be reproduced...

Page 3: ...iagram 5 3 6 Signal Connection Current Loop 4 3 5 Testing the Installation 4 3 4 Cabling to the CIO DAC I 3 3 3 Installing the CIO DAC I in the Computer 2 3 2 Selecting the Base Address 2 3 1 Initial...

Page 4: ...This page is blank...

Page 5: ...containing channel information to two control registers The control register is double buffered so a DAC s output is not updated until both bytes first low byte then high byte are written The CIO DAC...

Page 6: ...et BASE ADDRESS 3 2 Selecting the Base Address Unless there is already a board in your system that uses address 300h 768 decimal leave the switches as they are set at the factory In the following exam...

Page 7: ...0 021 EGA 2C0 2CF 8237 DMA 1 000 00F FUNCTION HEX RANGE FUNCTION HEX RANGE The CIO DAC I BASE ADDRESS switch can be set for address in the range of 000 3FEh so it should not be hard to find a free add...

Page 8: ...a for prototyping circuitry CIO SPADE 50 4 X 16 in screw terminal board with on board prototyping area CIO TERMINAL 37 position 4 X 4 in screw terminal board CIO MINI37 5 foot shielded round cable wit...

Page 9: ...or 36V being typical choices Figure 3 2 Basic Current Loop The 4 to 20 mA loop can be configured with either a floating power supply Figure 3 3 or a floating load Figure 3 4 Figure 3 3 I Loop Floatin...

Page 10: ...rmation on the CIO TERMINAL CIO SPADE50 and CIO MINI37 screw terminal boards in the Measurement Computing catalog Figure 3 5 CIO DAC16 I Connector Figure 3 6 CIO DAC08 I Connector 6 12V 19 GND 18 12V...

Page 11: ...ress or BASE ADDRESS is determined by the setting of a bank of switches on the board The register descriptions all follow the format A0 A1 A2 A3 A4 A5 A6 A7 0 1 2 3 4 5 6 7 the numbers along the top r...

Page 12: ...ster is written to second A write to this register updates the output of the selected D A with all 12 bits of the D A code contained in the two registers BASE 1 D4 D3 D2 D1 MSB CH0 CH1 CH2 CH3 0 1 2 3...

Page 13: ...the output on channel 3 to 11 890625mA CODE 11 890625mA 4 16 4095 2020 The digital code for 2020 is 0111 1110 0100 To this you would add the value for channel 3 0011 as the upper nibble for the secon...

Page 14: ...to 36V D A pacing Software paced Data transfer Software Offset error Adjustable to zero Gain error Adjustable to zero Differential nonlinearity 1 LSB max Integral nonlinearity 1 LSB max Monotonicity G...

Page 15: ...nd other normative documents EU EMC Directive 89 336 EEC Essential requirements relating to electromagnetic compatibility EU 55022 Class B Limits and methods of measurements of radio interference char...

Page 16: ...508 946 5100 Fax 508 946 9500 E mail info measurementcomputing com www measurementcomputing com Measurement Computing Corporation 10 Commerce Way Suite 1008 Norton Massachusetts 02766 508 946 5100 Fax...

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