MAX4888A/MAX4889A
5.0Gbps PCI Express Passive Switches
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9
Detailed Description
The MAX4888A/MAX4889A high-speed passive switch-
es route PCIe data between two possible destinations.
The MAX4888A/MAX4889A are ideal for routing PCIe sig-
nals to change the system configuration. For example, in
a graphics application, the MAX4888A/MAX4889A create
two sets of eight lanes from a single 16-lane bus. The
MAX4888A/MAX4889A feature a single digital control
input (SEL) to switch signal paths.
The MAX4888A/MAX4889A are fully specified to oper-
ate from a single 3.0V to 3.6V power supply and also
operate down to 1.65V.
Digital Control Input (SEL)
The MAX4888A/MAX4889A provide a single digital
control input (SEL) to select the signal path between
the COM__ and NO__/NC__ channels. The truth tables
for the MAX4888A/MAX4889A are depicted in the
Functional Diagrams/Truth Table section. Drive SEL
rail-to-rail to minimize power consumption.
Analog Signal Levels
The MAX4888A/MAX4889A accept standard PCIe sig-
nals to a maximum of V+ - 1.2V. Signals on the COM_+
channels are routed to either the NO_+ or NC_+ chan-
nels, and signals on the COM_- channels are routed to
either the NO_- or NC_- channels. The MAX4888A/
MAX4889A are bidirectional switches, allowing COM__,
NO__, and NC__ to be used as either inputs or outputs.
CAPACITANCE
METER
NC_ or
NO_
COM_
GND
SEL
V
IL
OR V
IH
0.1
μ
F
3.3V
V+
MAX4888A/MAX4889A
Figure 4. Channel Off-/On-Capacitance
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED BETWEEN ANY TWO PAIRS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
3.3V
V
OUT
V+
SEL
NC_
COM_
NO_
V
IN
MAX4888A/MAX4889A
OFF-ISOLATION = 20log
V
OUT
V
IN
ON-LOSS = 20log
V
OUT
V
IN
CROSSTALK = 20log
V
OUT
V
IN
NETWORK
ANALYZER
50
Ω
50
Ω
50
Ω
50
Ω
MEAS
REF
0.1
μ
F
0V OR V+
50
Ω
GND
Figure 3. On-Loss, Off-Isolation, and Crosstalk
Test Circuits/Timing Diagrams (continued)