DS80C400 Network Microcontroller
57 of 96
CSR Register:
Flow Control
Register Address:
1Ch
Bit Names:
31 PAUSE
[15:8]
24
23 PAUSE
[7:0]
16
15
—
—
—
—
—
—
—
—
8
7
—
—
—
—
—
PCF FCE BUSY
0
Reset State:
31 0 0 0 0 0 0 0 0
24
23 0 0 0 0 0 0 0 0
16
15
0
0
0
0
0
0
0
0
8
7
0
0
0
0
0
0 0 0
0
PAUSE[15:0], Pause Time [15:0].
These bits are only valid in full-duplex mode. These 16 bits contain the value
that is passed in the pause time field when a pause-control frame is generated. The format for the pause-control
frame is shown in
Figure 3
.
PCF, Pass
Pause-Control Frame.
This bit is valid for full-duplex mode only. This bit instructs the MAC whether or
not to set the packet filter bit for pause-control frames.
0 = MAC decodes (if FCE = 1) but does not set the receive status word packet-filter bit (default)
1 = MAC decodes (if FCE = 1) and sets the packet-filter bit = 1 for pause-control frames
FCE,
Flow Control Enable
0 = MAC flow control is disabled (default)
1 = MAC flow control enabled; pause-control frame for full-duplex, back-pressure for half-duplex
BUSY,
Flow Control Busy.
The BUSY bit is only valid in full-duplex mode. The BUSY bit should read logic 0
before initiating a pause-control frame. The BUSY bit should be set to logic 1 to initiate a pause-control frame.
Upon successful transmission of a pause-control frame, the BUSY bit returns to logic 0.
0 = no pause-control frame currently being transmitted (default)
1 = initiate a pause-control frame
Figure 3. Pause-Control Frame
ETHERNET FRAME
PREAMBLE
SFD
01 80 C2 00 00 01
SOURCE ADDRESS
88 08
00 01
PAUSE TIME (2)
PAD (42
)
CRC-32
(7) (1)
(6)
(6)
(2)
(46)
(4)