MAX32660 User Guide
Maxim Integrated
Page 52 of 195
. For the 96MHz Relaxation Oscillator as the system clock, the
.clkdiv
field should be set to 96 (0x60). If
another clock source is set as the system clock, this field must be adjusted to meet the target 1MHz for
f
FLC_CLK
.
Equation 5-1: Flash Controller Clock Frequency
𝑓
𝐹𝐿𝐶_𝐶𝐿𝐾
=
𝑓
𝑆𝑌𝑆𝐶𝐿𝐾
𝐹𝐿𝐶_𝐶𝐿𝐾𝐷𝐼𝑉. 𝑐𝑙𝑘𝑑𝑖𝑣
= 1𝑀𝐻𝑧
5.3.2
Lock Protection
The Flash Controller provides a locking mechanism to prevent accidental writes and erases. Each write or erase requires the
.unlock
field be set to 0x2 prior to starting the operation. Writing any other value to the
unlock
field
results in the flash remaining locked.
Note: If a write, page erase or mass erase operation is started and the unlock code was not set to 0x2, the Flash Controller
hardware sets the access fail flag,
.access_fail, to indicate an access violation occurred.
5.3.3
Flash Write Width
The Flash Controller supports write widths of either 32-bits or 128-bits. Selection of the flash write width is controlled with
the
.width
field and defaults to 128-bit width on all forms of reset. Setting
.width
to 1 selects 32-bit write
widths.
In 128-bit width mode, the target address bits
[3:0] are ignored resulting in 128-bit alignment. In 32-bit width
[1:0] are ignored for 32-bit address alignment. If the desired target address is not
128-bit aligned (
[3:2]
≠
0), 32-bit width mode is required.
Table 5-2: Valid Addresses for 32-bit and 128-bit Internal Flash Writes
FLC_ADDR[31:0]
Bit Number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32-bit Write
0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x 0 0
128-bit Write
0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x 0 0 0 0
