MAX32660 User Guide
Maxim Integrated
Page 54 of 195
5.3.6
Mass Erase
Mass erase clears the internal flash memory. This operation requires the JTAG debug port to be enabled to perform the
operation. If the JTAG debug port is not enabled a mass erase operation cannot be performed. Perform the following steps
to mass erase the internal flash:
1.
Set
.unlock
to 0x2 to unlock the internal flash.
2.
Read the
.busy
bit until it returns 0.
3.
Set
.erase_code
to 0xAA for mass erase.
4.
Set
.mass_erase
to 1 to start the mass erase operation.
5.
.busy
bit is set by the Flash Controller while the mass erase is in progress and the
.mass_erase
.busy
are cleared by the Flash Controller when the mass erase is complete.
6.
.done
is set by the Flash Controller when the mass erase completes. If an error occurred, the
.access_fail
flag is set. These bits generate a Flash Controller IRQ if the interrupt enable bits are set.
Note: Mass erase requires the JTAG debug port to be enabled, if the JTAG debug port is disabled on the device an access fail
error is generated
.access_fail = 1).
5.4
Flash Controller Registers
The FLC base peripheral address is 0x4002 9000. Refer to
Table 3-1: APB Peripheral Base Address Map
for the addresses of
all APB mapped peripherals.
Table 5-4: Flash Controller Registers, Offsets, Access and Descriptions
Offset
Register Name
Access Description
[0x0000]
R/W
Flash Controller Address Pointer Register
[0x0004]
R/W
Flash Controller Clock Divisor Register
[0x0008]
R/W
Flash Controller Control Register
[0x0024]
R/W1C Flash Controller Interrupt Register
[0x0030]
R/W
Flash Controller Data Register 0
[0x0034]
R/W
Flash Controller Data Register 1
[0x0038]
R/W
Flash Controller Data Register 2
[0x003C]
R/W
Flash Controller Data Register 3
Table 5-3. Flash Controller Address Pointer Register
Flash Address Register
FLC_ADDR
[0x00]
Bits
Name
Access
Reset
Description
31:0
addr
R/W
0
Flash Address
This field contains the target address for a write operation. A valid internal flash
memory address is required for all write operations. The reset default is always
address 0x00000000.
Table 5-4. Flash Controller Clock Divisor Register
Flash Controller Clock Divisor Register
FLC_CLKDIV
[0x04]
Bits
Name
Access
Reset
Description
31:8
-
RO
-
Reserved for Future Use
Do not modify this field.
