DS3234
Extremely Accurate SPI Bus RTC
with Integrated Crystal and SRAM
Maxim Integrated | 11
www.maximintegrated.com
When
RST
is active due to a power-fail condition (see
Table 1), SPI operations are inhibited while the TCXO
and RTC continue to operate. When
RST
is active due
to a pushbutton event, it does not affect the operation
of the TCXO, SPI interface, or RTC functions.
Real-Time Clock
With the clock source from the TCXO, the RTC provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is auto-
matically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates
in either the 24-hour or 12-hour format with an
AM
/PM
indicator.
The clock provides two programmable time-of-day
alarms and a programmable square-wave output. The
INT
/SQW pin either generates an interrupt due to alarm
condition or outputs a square-wave signal and the
selection is controlled by the bit INTCN.
SRAM
The DS3234 provides 256 bytes of general-purpose
battery-backed read/write memory. The SRAM can be
written or read whenever V
CC
is above either V
PF
or
V
BAT
.
Address Map
Figure 1 shows the address map for the DS3234 time-
keeping registers. During a multibyte access, when the
address pointer reaches the end of the register space
(13h read, 93h write), it wraps around to the beginning
(00h read, 80h write). The DS3234 does not respond to
a read or write to any reserved address, and the inter-
nal address pointer does not increment. Address point-
er operation when accessing the 256-byte SRAM data
is covered in the description of the SRAM address and
data registers. On the falling edge of
CS
, or during a
multibyte access when the address pointer increments
to location 00h, the current time is transferred to a sec-
ond set of registers. The time information is read from
these secondary registers, while the internal clock reg-
isters continue to increment normally. If the time and
date registers are read using a multibyte read, this
eliminates the need to reread the registers in case the
main registers update during a read.
SPI Interface
The DS3234 operates as a slave device on the SPI seri-
al bus. Access is obtained by selecting the part by the
CS
pin and clocking data into/out of the part using the
SCLK and DIN/DOUT pins. Multiple byte transfers are
supported within one
CS
low period. The SPI on the
DS3234 interface is accessible whenever V
CC
is above
either V
BAT
or V
PF
.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Figure 1 illustrates
the RTC registers. The time and calendar data are set
or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in
binary-coded decimal (BCD) format. The DS3234 can
be run in either 12-hour or 24-hour mode. Bit 6 of the
hours register is defined as the 12- or 24-hour mode
select bit. When high, 12-hour mode is selected. In 12-
hour mode, bit 5 is the
AM
/PM bit with logic-high being
PM. In 24-hour mode, bit 5 is the 20-hour bit (20–23
hours). The century bit (bit 7 of the month register) is
toggled when the years register overflows from 99 to
00.
The day-of-week register increments at midnight.
Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the
time and date registers, the user buffers are synchro-
nized to the internal registers on the falling edge of
CS
or and when the register pointer rolls over to zero. The
time information is read from these secondary registers,
while the clock continues to run. This eliminates the
need to reread the registers in case the main registers
update during a read.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur when the last
bit of a byte is clocked in. Once the countdown chain is
reset, to avoid rollover issues the remaining time and
date registers must be written within 1 second. The 1Hz
square-wave output, if enabled, transitions high 500ms
after the seconds data transfer.
