Matrox Solios eA, Installation And Hardware Reference, Page: 68 / 196

68 Chapter 4: Matrox Solios hardware reference
Next valid frame/field and asynchronous reset modes
Matrox Solios eCL/XCL can operate in two modes: next valid frame/field mode
and asynchronous reset mode. In next valid frame/field mode, the board waits for
the next valid frame or field (as specified by the DCF file) before commencing the
grab.
In asynchronous reset mode, the board resets the video source to begin a new frame
when the trigger signal is received. The board uses an exposure timer signal to reset
the video source.
Trigger
When in either next valid frame/field mode, or in asynchronous reset mode, the
board accepts trigger input signals which allow image acquisition to be
synchronized with external events. For each PSG, you can program two auxiliary
signals as external trigger input signals. For each PSG, you can also program two
path-independent auxiliary signals as trigger input signals.
When received in TTL format directly, the signal must have a maximum
amplitude of 5 V. A signal over 2 V is considered high, while anything less than
0.8 V is considered low; the transition of 0.8 V to 2 V is considered to be the rising
edge.
If using the trigger to start acquisition, the trigger signal’s pulse width must be
greater than two pixels; if using the trigger to start the exposure timer, the trigger
signal’s pulse width must be greater than two clock periods of the timer. To
determine the timer period, take the inverse of the pixel or timer’s clock frequency,
respectively. For example, if the pixel frequency is 12.27 MHz, the minimum pulse
width is 2 x 1/12.27 MHz (approximately 163 nsec).
The opto-isolated trigger signals pass through an opto-coupler. The voltage
difference across the positive and negative components of the signal must be
between 4.06 V and 9.165 V for logic high, and between -5.0 V and 0.8 V for
logic low.