7
EVE2 TFT Module
5.2
SPI and QSPI communication
The EVE2 TFT Module is capable of communicating to hosts and microcontrollers through a quad serial parallel
interface (QSPI). Only SPI mode 0 is supported. The QSPI slave interface can operate up to 30MHZ, and can be
configured in SINGLE, DUAL or QUAD channel modes.
The SPI slave defaults to SINGLE channel mode operation, using MISO as output to the master and MOSI as input
from the master. The SPI slave can be configured to allow DUAL and QUAD channel modes by writing to register
REG_SPI_WIDTH while in single channel mode.
Table 4: SPI/QSPI Communication Configuration
REG_SPI_WIDTH[1:0]
Channel Mode
Data pins
Max bus speed
00
SINGLE - default mode
MISO, MOSI
30 MHz
01
DUAL
IO0, IO1
30 MHz
10
QUAD
IO0, IO1, IO2, IO3
25 MHz
11
Reserved
-
-
When DUAL/QUAD channel modes are enabled, the SPI data ports become unidirectional. SPI transactions will be
signified by CS going active low when DUAL/QUAD modes are active, and data ports are set as inputs.
Hence, for writing to the FT81x, the protocol is “WR-Command/Addr2, Addr1, Addr0, DataX, DataY, DataZ …” The
write operation is considered complete when CS goes inactive high.
For reading from the FT81x, the protocol is “RD-Command/Addr2, Addr1, Addr0, Dummy-Byte, DataX, DataY,
DataZ”. However as the data ports are now unidirectional, a change of port direction will occur before DataX is
clocked out of the FT81x. Therefore it is important that the firmware controlling the SPI master changes the SPI
master data port direction to “input” after transmitting Addr0. The FT81x will not change the port direction till it
starts to clock out DataX. Hence, the Dummy-Byte cycles will be used as a change-over period when neither the
SPI master nor slave will be driving the bus; the data paths thus must have pull-ups/pull-downs. The SPI slave from
the FT81x will reset all its data ports’ direction to input once CS goes inactive high (i.e. at the end of the current
SPI master transaction).
The below diagram depicts the behaviour of both the SPI master and slave in the master read case.
Figure 7: SPI Master and Slave bus behaviour
