EVE2 TFT Module
6
4
Communication Model
4.1
Programming Model
The FT81X appears to the host MCU as a memory-mapped SPI device. The host MCU sends commands and data
over the serial protocol described in the data sheet.
4.2
General Software Architecture
The software architecture can be broadly classified
into layers such as custom applications,
graphics/GUI manager, video manger, audio
manager, drivers etc. FT81X higher level graphics
engine commands and co-processor engine widget
commands are part of the graphics/GUI manager.
Control & data paths of video and audio are part of
video manager and audio manager. Communication
between graphics/GUI manager and the hardware
is via the SPI driver. Typically the display screen shot
is constructed by the custom application based on
the framework exposed by the graphics/GUI
manager.
Figure 5: EVE 2 Programmer model
5
Communication Interface
5.1
SPI Interface Timing Specification
Figure 6: SPI Timing Diagram
Table 3: SPI Timing Signals
Parameter
Description
VCCIO = 3.3V
Units
Min
Max
Tsclk
SPI Clock Period (SINGLE/DUAL mode)
33.3
ns
Tslck
SPI clock Period (QUAD mode)
40
ns
Tsclkl
SPI clock low duration
13
ns
Tsclkh
SPI clock high duration
13
ns
Tsac
SPI access time
3
ns
Tisu
Input Setup
3
ns
Tih
Input hold
0
ns
Tzo
Output enable delay
11
ns
Toz
Output disable delay
10
ns
Tod
Output data delay
11
ns
Tcsnh
CSN hold time
0
ns
