48
IC715:AK5380
6. IC DATA
No.
Pin Name
I/O
Description
1
AINR
I
Rch Analog Input Pin
2
A INL
I
Lch Analog Input Pin
3
NC
-
NC Pin
No internal bonding.
4
VCOM
O
Common Voltage Output Pin
Normally connected to AGND with a 0.1 F ceramic capacitor in parallel with an
electrolytic capacitor less than 2.2 F.
5
AGND
-
Analog Ground Pin, 0V
6
V A
-
Analog Power Supply Pin, +4.5 +5.5V
7
V D
-
Digital P ower Supply Pin, +2.7 +5.5V(fs=48kHz), +4.5 +5.5V(fs=96kHz)
8
DGND
-
Digital Ground Pin, 0V
9
SDTO
O
Serial Data Output Pin
Data bits are presented MSB first, in 2’s complement format.
This pin is “L ” in the power-down mode.
10
LRCK
I
Left/Right Channel Select Pin
The fs clock is input to this pin.
11
M CL K
I
Master Clock Input Pin
12
SCLK
I
Serial Data Input Pin
Output data is clocked out on the falling edge of SCLK.
13
PDN
I
Power-Down Pin
When “L ”, the circuit is in power-down mode.
The AK5380 should always be reset upon power-up.
14
DI F
I
Serial Interface Format Pin
“L ”: MSB justified, “H”: I
2
S
15
TTL
I
Digital Input Level Select Pin
“L ”: CMOS level (VD=2.7
5.5V), “H”: TTL level (VD=4.5
5.5V)
16
TST
I
Test Pin (Internal pull-down pin)
This pin should be left open.
1
AINR
AINL
VCOM
NC
AGND
VA
VD
DGND
Top
View
2
3
4
5
6
7
8
TST
TTL
PDN
DIF
SCLK
MCLK
LRCK
SDTO
16
15
14
13
12
11
10
9
Pin Assignment
Pin Function
IC504:TC9481
Pin Function
Summary of Contents for SR5300
Page 6: ...4 MEMO ...
Page 7: ...5 6 2 WIRING DIAGRAM ...
Page 8: ...7 8 3 BLOCK DIAGRAM ...
Page 9: ...9 10 4 SCHEMATIC DIAGRAM ...
Page 10: ...11 12 ...
Page 11: ...13 14 ...
Page 12: ...15 16 ...
Page 13: ...17 18 ...
Page 14: ...19 20 ...
Page 15: ...21 22 ...
Page 16: ...23 24 ...
Page 17: ...25 26 ...
Page 23: ...37 38 D701 703 IC712 IC710 IC703 D706 Q705 Q704 Q702AFL Q702 Q702AFR IC713 DSP ...
Page 25: ...41 INPUT 1 IC401 IC404 IC403 INPUT 2 D501 D502 ...
Page 27: ...43 IC808 IC806 IC805 IC804 IC802 IC803 IC807 S VIDEO MULTI CONTROL ...
Page 28: ...44 Q822 D870 D871 Q821 Q871 Q870 Q822A D873 D884 D872 VIDEO SPEAKER A ...