72
PIN
PORT
NAME
I/O
INITIAL
FUNCTION
NOR
MAL
STBY
66
AN7
KEY_1
I
I
-
KEY INPUT AD INPUT
67
AN6
KEY_2
I
I
-
KEY INPUT AD INPUT
68
AN5
KEY_3
I
I
-
KEY INPUT AD INPUT
69
AN4
TRAY_IN_SW
I
I
-
TRAY OPEN CLOSING TRIGGER INPUT AD INPUT
70
P0_4
DIR_DO
O
I
L
DIR IC DATA OUTPUT
71
P6_2
DIR_DI
I
I
-
DIR IC DATA INPUT
72
P6_1
DIR_CL
O
I
L
DIR IC CLOCK OUTPUT
73
P0_5
DIR_CE
O
I
L
DIR IC CHIP ENABLE OUTPUT
74
AN1
MODEL_SEL_1
I
I
-
MODEL SELECTION AD INPUT
75
VSS
VSS
-
-
-
GND
76
AN0
MODEL_SEL_2
I
I
-
MODEL SELECTION AD INPUT
77
VREF
VREF
-
-
-
3.3V
78
VCC
VCC
-
-
-
3.3V
79
P3_7
USB_NMI
I
I
-
USB IC STANDBY DETECTION
80
P3_5
SCL
O
I
H
IIC CLOCK OUTPUT
EPM3032A (Programmable Logic Device) (MAIN :U203)
6 or 10
6 or 10
INPUT/GCLRn
6 or 10 Output Enables
(1)
6 or 10 Output Enables
(1)
16
36
36
16
I/O
Control
Block
LAB C
LAB D
I/O
Control
Block
6 or 10
16
36
36
16
I/O
Control
Block
LAB A
Macrocells
1 to 16
LAB B
I/O
Control
Block
6 or 10
PIA
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
2 to 16 I/O
2 to 16 I/O
2 to 16 I/O
2 to 16 I/O
2 to
16
2 to
16
2 to
16
2 to
16
2 to 16
2 to 16
2 to 16
2 to 16
Macrocells
17 to 32
Macrocells
33 to 48
Macrocells
49 to 64
Summary of Contents for SA-KI-PEARL-LITE/N1B
Page 35: ...10 Click the E P R 11 Click the OK 35...
Page 46: ...46 Personal notes...
Page 74: ...74 TE7022L MAIN U632 TE7022L Pin Descriptions...
Page 75: ...75 TE7022L Pin Descriptions...
Page 80: ...80 2 FL DISPLAY FLD 13 BT 237INK FRONT Z0701 PIN CONNECTION GRID ASSIGNMENT q R7...
Page 81: ...81 ANODE CONNECTION...