38
No.
Pin Name
I/O
Pin Function and Description
1
SDATA
I
Serial Audio Data Input - two’s complement MSB-first serial data is input on this pin.
The data is clocked into the CS4334/5/8/9 via internal or external SCLK, and the channel
is determined by LRCK.
2
DEM/SCLK
I
De-Emphasis/External Serial Clock Input - used for de-emphasis filter control or exter-
nal serial clock input.
3
LRCK
I
Left/Right Clock - determines which channel is currently being input on the Audio Serial
Data Input pin, SDATA.
4
MCLK
I
Master Clock - frequency must be 256x, 384x, or 512x the input sample rate in BRM and
either 128x or 192x the input sample rate in HRM.
5
AOUTR
O Analog Right Channel Output - typically 3.5 Vp-p for a full-scale input signal.
6
AGND
I
Analog Ground - analog ground reference is 0V.
7
VA
I
Analog Power - analog power supply is nom5V.
8
AOUTL
O Analog Left Channel Output - typically 3.5 Vp-p for a full-scale input signal.
SERIAL DATA INPUT
SDATA
AOUTL
ANALOG LEFT CHANNEL OUTPUT
DE-EMPHASIS / SCLK
DEM/SCLK
VA
ANALOG POWER
LEFT / RIGHT CLOCK
LRCK
AGND
ANALOG GROUND
MASTER CLOCK
MCLK
AOUTR
ANALOG RIGHT CHANNEL OUTPUT
7
2
6
3
5
4
8
1
LRCK
3
SDATA
1
DEM/SCLK
2
MCLK
4
VA
AOUTL
8
AOUTR
5
Serial Input
Interface
Interpolator
Interpolator
De-emphasis
Modulator
Modulator
DAC
DAC
Voltage Reference
Analog
Low-Pass
Filter
Analog
Low-Pass
Filter
7
AGND
6
∆∑
∆∑
Q303:BU2630FV
12. MICROPROCESSOR AND IC DATA
Pin descriptions
Q381:CS4338
Summary of Contents for PMD351
Page 8: ...6 ADJUSTMENT POINT COMPONENT SIDE...
Page 16: ...14 Personal notes...
Page 17: ...15 16 TO CASSETTE MECHA TO CD MECHA TO CD MECHA 8 WIRING DIAGRAM...
Page 27: ...35 PY03 PY13 QY01 QY02 QY01 PY23 PY33...
Page 28: ...36 PS03 PT03 PG03 PV03 QV01 PP01 QR01...
Page 36: ...44 QU51 PD784217AGC 192 8EU...
Page 41: ...51...