D/A
Interface
Error
Corrector
32K
RAM
Digital
OUT
Sub Code
Processor
Clock
Generator
Asymmetry
Corrector
Digital
PLL
Digital
CLV
CPU
Interface
Servo
Auto
Sequencer
Signal processor biock
RFAC
ASYO
ASYE
BIAS
XPCK
FILO
FILI
PCO
CLTV
MDP
LOCK
SENS
DATA
XLAT
CLOK
SCOR
SBSO
EXCK
SCSY
SQSO
SQCK
XRST
TEST
TES1
PWMI
ASYI
FSTO
C4M
Servo block
SERVO
Interface
MIRR
DFCT
FOK
SERVO DSP
FOCUS SERVO
TRACKING
SERVO
SLED SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
RFDC
CE
TE
SE
FE
VC
IGEN
OPAmp
Analog SW
A/D
Converter
ADIO
FFDR
FRDR
TFDR
TRDR
SFDR
SRDR
SOUT
SOCK
XOLT
SCLK
COUT
SSTP
ATSK
MIRR
DFCT
FOK
XTAI
XTAO
XTSL
V16M
VPCO
VCTL
MUTE
BCK
PCMD
LRCK
C2PO
WDCK
DOUT
MD2
WFCK
EMPH
GFS
XUGF
EFM
demodurator
16
27
50
48
49
57
62
12
23
24
25
52
53
54
55
4
5
6
7
15
76
77
78
79
80
40
39
38
41
42
43
44
46
29
30
34
31
32
33
8
9
19
20
21
22
26
73
74
75
2
37
36
3
14
17
67
65 66
10
11 13 68
58
59 60
69
71 72
63
64
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
I
I
I
I
I
O
I
I/O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I
I/O
O
I
O
O
O
O
O
O
O
I
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Power supply.
System reset. Reset when low.
Mute input (low: off, high: on)
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
SENS output to CPU.
SENS serial data readout clock input.
Anti-shock input/output.
WFCK output.
XUGF output. MNTO or RFCK is output by switching with the command.
XPCK output. MNTI is output by switching with the command.
GFS output. MNT2 or XROF is output by switching with the command.
C2P0 output. MNT3 or GTOP is output by switching with the command.
Outputs a high signal when either subcode sync SO or S1 is detected.
4.2336MHz output. 1/4 frequency division output for V16M in CAV-W mode
or variable pitch mode.
Word clock output. f = 2Fs. GRSCOR is output by the command switching.
Digital GND.
Track count ,signal I/O.
Mirror signal I/O.
Detect signal I/O.
Focus OK signal I/O.
Spindle motor external control input.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when LKIN=1.
Spindle motor servo control output.
Disc innermost track detection signal input.
2/3 frequency division output for XTAI pin.
Digital power supply.
Sled drive output.
Sled drive output.
Tracking drive output.
Tracking drive output.
Focus drive output.
Focus drive output.
Digital GND.
Test. Normally, GND.
DV
DD
0
XRST
MUTE
DATA
XLAT
CLOK
SENS
SCLK
ATSK
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
C4M
WDCK
DV
SS
0
COUT
MIRR
DFCT
FOK
PWMI
LOCK
MDP
SSTP
FSTO
DV
DD
1
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
DV
SS
1
TEST
Symbol I/O
Description
-
-
-
-
-
-
-
Pin
NO.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
I
I
I
I
I
I
I
O
-
I
O
I
I
I
O
I
O
I
I
I/O
O
I
I
O
O
O
O
O
I
I
O
Analog
-
1, 0
Analog
1, Z, 0
1, 0
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Test. Normally, GND.
Center voltage input.
Focus error signal input.
Sled error signal input.
Tracking error signal input.
Center servo analog input.
RF signal input.
Test. No connected.
Analog GND.
Constant current input for operational amplifier.
Analog power supply.
EFM full-swing output. (Iow = Vss, high = VDD)
Asymmetry comparator voltage input.
EFM signal input.
Analog GND.
Multiplier VCO1 control voltage input.
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Master PLL charge pump output.
Analog power supply.
Asymmetry circuit constant current input.
Wide-band EFM PLL VC02 control voltage input.
Wide-band EFM PLL VC02 oscillation output. Serves as
wide-band EFM PLL clock input by switching with the command.
Wide-band EFM PLL charge pump output.
Digital power supply.
Asymmetry circuit on/off (low = oft, high = on).
Digital Out on/oft control (low = off, high = on).
Digital Out output.
D/A interface. LR clock output. f = Fs
D/A interface. Serial data output (two's complement, MSB first).
D/A interface. Bit clock output.
Outputs a high signal when the playback disc has emphasis, and a low
signal when there is no emphasis.
Crystal selection input. Low when the crystal is 16.9344MHz; high when it is
33.8688MHZ.
Digital GND.
Crystal oscillation circuit input. When the master clock is input externally,
input it from this pin.
Crystal oscillation circuit output.
TES1
VC
FE
SE
TE
CE
RFDC
ADIO
AV
SS
0
IGEN
AV
DD
0
ASYO
ASYI
RFAC
AV
SS
1
CLTV
FILO
FILI
PCO
AV
DD
1
BIAS
VCTL
V16M
VPCO
DV
DD
2
ASYE
MD2
DOUT
LRCK
PCMD
BCK
EMPH
XTSL
DV
SS
2
XTAI
XTAO
Symbol I/O
Description
-
-
-
-
-
-
-
-
Pin
NO.
73
74
75
76
77
78
79
80
O
O
O
O
I
I
O
I
1, 0
1, 0
1, 0
1, 0
1, 0
Serial data output in servo block.
Serial data readout clock output in servo block.
Serial data latch output in servo block.
Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output.
SQSO readout clock input.
GRSCOR resynchronization input.
Sub-Q P to W serial output.
SBSO readout clock input.
SOUT
SOCK
XOLT
SQSO
SQCK
SCSY
SBSO
EXCK
Symbol I/O
Description
Notes)
* PCMD is a MSB first, two's complement output.
* GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
* XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection.
* XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal
Atransition point coincide.
* The GFS signal goes high when the frame sync and the insertion protection timing match.
* RFCK is derived from the crystal accuracy, and has a cycle of 136us. (during normal speed)
* C2PO represents the data error status.
* XROF is generated when the 32K RAM exceeds the +-28F jitter margin.
7
8
QD01 : CXD2585Q
5
3
2Z
2Y
1Z
1Y
2A
1A
7
6
1
2
5
3
2Z
2Y
1Z
1Y
1A
2A
7
6
1
1
2
3
4
8
7
6
5
1Z
1Y
1A
GND
V
CC
2Z
2Y
2A
QT52 : SN75158
Summary of Contents for PMD330
Page 11: ...17 18 8 SCHEMATIC DIAGRAM...