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STA309A_ST (MAIN : IC102)
STA309A_ST Block Diagram
STA309A_ST Pin Discription
Pin
Type
Name
Description
1
5-V tolerant TTL input buffer
MVO/DSD_CLK Master volume override / DSD input clock
6
5-V tolerant TTL input buffer
SDI_78/DSD_6 Input serial data channels 7 & 8 / DSD input channel 6
7
5-V tolerant TTL input buffer
SDI_56/DSD_5 Input serial data channels 5 & 6 / DSD input channel 5
8
5-V tolerant TTL input buffer
SDI_34/DSD_4 Input serial data channels 3 & 4 / DSD input channel 4
9
5-V tolerant TTL input buffer
SDI_12/DSD_3 Input serial data channels 1 & 2 / DSD input channel 3
10
5-V tolerant TTL input buffer
LRCKI/DSD_2 Input left/right clock / DSD input channel 2
11
5-V tolerant TTL input buffer
BICKI/DSD_1
Input serial clock / DSD input channel 1
15
5-V tolerant TTL schmitt trigger
input buffer
RESET
Global reset
16
CMOS input buffer with pull-down PLL_BYPASS
Bypass phase locked loop
17
CMOS input buffer with pull-down SA
Select address (I2C)
18
Bidirectional buffer: 5-V tolerant
TTL schmitt trigger input; 3.3-V
capable 2mA slew-rate controlled
output.
SDA
Serial data (I2C)
19
5-V tolerant TTL schmitt trigger
input buffer
SCL
Serial clock (I2C)
20
5-V tolerant TTL schmitt trigger
input buffer
XTI
Crystal oscillator input (clock input)
21
Analog pad
FILTER_PLL
PLL filter
Pin connections
STA309A
10/67
Doc ID 13855 Rev 4
2
Pin connections
Figure 3.
Pin connection (top view)
Table 2.
Pin description
Pin
Type
Name
Description
1
5-V tolerant TTL input buffer MVO/DSD_CLK
Master volume override/
DSD input clock
6
5-V tolerant TTL input buffer SDI_78/DSD_6
Input serial data channels 7 & 8/
DSD input channel 6
7
5-V tolerant TTL input buffer SDI_56/DSD_5
Input serial data channels 5 & 6/
DSD input channel 5
8
5-V tolerant TTL input buffer SDI_34/DSD_4
Input serial data channels 3 & 4/
DSD input channel 4
9
5-V tolerant TTL input buffer SDI_12/DSD_3
Input serial data channels 1 & 2/
DSD input channel 3
10
5-V tolerant TTL input buffer LRCKI/DSD_2
Input left/right clock/
DSD input channel 2
11
5-V tolerant TTL input buffer BICKI/DSD_1
Input serial clock/
DSD input channel 1
15
5-V tolerant TTL schmitt
trigger input buffer
RESET
Global reset
16
CMOS input buffer with
pull-down
PLL_BYPASS
Bypass phase locked loop
1
2
3
5
6
4
7
8
9
10
27
11
28 29 30 31 32
59 58 57 56
54
55
53 52 51 50 49
43
42
41
39
38
40
48
47
46
44
45
SDI_78
NC
GND
GND
MVO
VDD
BICKI
LRCKI
SDI_12
SDI_56
SDI_34
NC
GNDA
VDDA
CKOUT
GND
NC
VDD
OUT8_B
OUT8_A
OUT7_B
OUT7_A
VDD
SDO_34
SDO_12
LRCKO
NC
BICKO
GND
VDD
EAPD
OUT1_A
OUT1_B
OUT3_A
OUT3_B
OUT4_A
OUT5_A
OUT5_B
OUT4_B
OUT2_A
OUT2_B
NC
VDD
GND
STA308APINCON
22 23 24 25 26
60
GND
61
NC
62
SDO_56
63
SDO_78
64
PWDN
SA
SDA
SCL
XTI
FILTER_PLL
17 18 19 20 21
37
36
34
33
35
NC
GND
OUT6_A
OUT6_B
VDD
12
13
14
15
16
PLLB
RESET
NC
VDD
GND
STA309A
Block diagram
Doc ID 13855 Rev 4
9/67
1
Block diagram
Figure 1.
Block diagram
Figure 2.
Channel signal flow
OUT1A/B
OUT2A/B
OUT3A/B
OUT4A/B
OUT5A/B
OUT6A/B
OUT7A/B
OUT8A/B
LRCKI
BICKI
SDI12
SDI34
SDI56
SDI78
SA
SERIAL
DATA
IN
I
2
C
CHANNEL
MAPPING
VARIABLE
OVER-
SAMPLING
TREBLE,
BASS, EQ
(BIQUADS)
VOLUME
LIMITING
SDO78
SDO12
SDO34
SDO56
OVERSAMPLING
VARIABLE
DOWN-
SAMPLING
POWER
DOWN
PWDN EAPD
PLL
PLLB
XTI
CKOUT
SCL SDA
LRCKO
BICKO
MVO
SERIAL
DATA
OUT
SYSTEM
CONTROL
SYSTEM TIMING
DDX
1x,2x,4x
Interp
Biquads
B/T
Volume
Limiter
2x
Interp
Distortion
Compensation
NS
C_Con
PWM
DDX
Output
Interp_Rate
8 Inputs
From I2S
DSD
Conversion
6 Inputs
From DSD
Mapping/
Mix #1
DSDE
Mix #2
PreScale
High-Pass
Filter
Biquad
#2
Biquad
#3
Biquad
#4
Biquad
#5
Biquad
#6
Biquad
#7
Biquad
#8
Bass
Hard Set to
-18dB when
AutoMode EQ
(AMEQ)
Hard Set Coeffecients when AutoMode EQ
(AMEQ)
Hard Set
Coeffecients when
AutoMode
Bass Management
Crossover
(AMBMXE)
Hard Set
Coeffecients when
DeEmphasis
Enabled
(DEMP)
From
Mix#1
Engine
Or
Previous
Channel
Biquad#10
Output
(CxBLP)
To
Mix#2
Engine
Treble
User Progammable
Biquad #1 when
High-Pass Bypassed
(HPB)
User Programmable
Biquads #9 and #10
When Tone Bypassed
(CxTCB)
92