118
PM01 / QN01: ADV7310
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
V
DD_IO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Y2
Y3
Y0
Y1
Y4
Y5
Y6
Y7
V
DD
DGND
Y8
Y9
C2
C0
C1
S_BLAN K
R
SET1
V
REF
COMP1
DAC A
DAC B
DAC C
V
AA
AGND
DAC D
DAC E
DAC F
COMP2
R
SET2
EXT_LF
RESET
C3
C4
I
2
C
ALSB
SD
A
SCLK
P_HSYNC
P_VSYNC
P_BLANK
C5
C6
C7
C8
C9
R
T
C_SCR_TR
CLKIN_A
GND_IO
CLKIN_B
S9
S8
S7
S6
S5
DGND
V
DD
S4
S3
S2
S1
S0
S_HSYNC
S_VSYNC
ADV7310/ADV7311
CLKIN_A
CLKIN_B
HSYNC
VSYNC
BLANK
Y9–Y0
C9–C0
S9–S0
TIMING
GENERATOR
PLL
O
V
E
R
S
A
M
P
L
I
N
G
I
2
C
INTERFACE
D
E
M
U
X
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE FILTERS
SD TEST PATTERN
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PROGRAMMABLE
RGB MATRIX
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
ADV7310/
ADV7311
Summary of Contents for DV9500
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Page 104: ...102 PT01 A QW82 QW83 QW01 QW81 QT01 QT51 PT01 B QT05 QT02 QT03 QW03 QT06 QW02 ...
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