Marantz DV9500, Service Manual

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103
15. MICROPROCESSOR AND IC DATA
QU01: H8S/2238R
Pin PORT Signal name I/O Contents of control
1 PE5/D5 V_PSW O Power supply control for VIDEO. L
2 PE6/D6 P/XI O Prograssive=H
3 PE7/D7 N.C. I
4 PD0/D8 DB4 O LCD DRIVER DATA 4
5 PD1/D9 DB5 O LCD DRIVER DATA 5
6 PD2/D10 DB6 O LCD DRIVER DATA 6
7 PD3/D11 DB7 O LCD DRIVER DATA 7
8 PD4/D12 E O Write enable for LCD DRIVER
9 PD5/D13 R/W O Read/Write for LCD DRIVER
10 PD6/D14 RS O Instruction for LCD DRIVER, Select data
11 PD7/D15 N.C. I
12 CVCC
13 PC0/A0 N.C. I
14 VSS
15 PC1/A1 STB_CONT O STB=L, POWER=H L
16 PC2/A2 STB_LED O LED for standby H
17 PC3/A3 FL_OFF_LED O LED for FL OFF H
18 PC4/A4 DHD I Head Phone detection port, Head Phone=L L
19 PC5/A5 BYPASS O A.DSP bypass signal, Bypass=L L
20 PC6/A6 N.C. I
21 PC7/A7 N.C. I
22 PB0/A8/TIOCA3 VRST_1 O Reset for CD0040AF L
23 PB1/A9/TIOCB3 VRST_2 O Reset for ADV7314/7310 L
24 PB2/A10/TIOCC3 VRST_3 O Reset for PD0280B (Scaler) L
25 PB3/A11/TIOCD3 VRST_4 O Reset for SiI9290 (HDMI) L
26 PB4/A12/TIOCA4 N.C. I
27 PB5/A13/TIOCB4 N.C. I
28 PB6/A14/TIOCA5 MC_RST O Reset for B/E L
29 PB7/A15/TIOCB5 B/EON I STB mode input port for B/E
30 PA0/A16 N.C. I
31 PA1/A17/TxD2 DATAO_OP O Data output port for B/E
32 PA2/A18/RxD2 DATAI_OP I Data input port for B/E
33 PA3/A19/SCK2 CLK_OP O Clock input port for B/E
34 P10/TIOCA0/DACK0/A20 IR_IN I Input capture
35 P11/TIOCB0/DACK1/A21 N.C. I
36 P12/TIOCC0/TCLKA/A22 N.C. I
37 P13/TIOCD0/TCLKB/A23 N.C. I
38 P14/TIOCA1/IRQ0 CS_OP I External interruption (Chip selection input port for B/E)
39 P15/TIOCB1/TCLKC /DFRES I Circumference IC.)
40 P16/TIOCA2/IRQ1 DSPREQ1 I Interruption REQ1 for ADSP
41 P17/TIOCB2/TCLKD N.C. I
42 AVSS GND
43 P97/DA1 N.C. I
44 P96/DA0 N.C. I
45 P47/AN7 BIT2 I Version distinction 3
46 P46/AN6 BIT1 I Version distinction 2
47 P45/AN5 BIT0 I Version distinction 1
48 P44/AN4 SELECT I Model distinction
49 P43/AN3 KEY4 I KEY_4 input
50 P42/AN2 KEY3 I KEY_3 input
51 P41/AN1 KEY2 I KEY_2 input
52 P40/AN0 KEY1 I KEY_1 input
53 Vref
54 AVCC
55 MD0
56 MD1
57 OSC2
58 OSC1
59 RES CPU_RST CPU reset signal
L:DV8500 H:OEM