Marantz DV7600, Service Manual

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44
IC11 : CS494003 (DSP)
Parallel or Serial
Host Interface
External Memory
Interface
Inter
nal Bus
32-Bit DSP Programmable
Multistandard
Audio Decoder
Compressed
Audio
Interface
PLL Clock
Manager
Shared Memor
y
Debug Port
GPIO and I/O
Controller
Digital
Audio
Interface
Digital
Audio
Interface
DSP C
DSP AB
Serial
Audio
Interface
SAI 0
SAI 1
SAI 2
SAI 3
DAO 0
DAO 1
Frame
Shifter
Input
Buffer
RAM
DSP
RAM
DSP
ROM
Parallel or Serial
Host Interface
FILT1 — Phase-Locked Loop Filter
Connects to an external filter for the on-chip phase-locked loop.
FILT2 — Phase Locked Loop Filter
Connects to an external filter for the on-chip phase-locked loop.
CLKIN, XTALI — External Clock Input/Crystal Oscillator Input
CS49400 clock input. This pin accepts an external clock input signal that is used to drive the
internal core logic. When in internal clock mode (CLKSEL == VSS), this input is connected to
the internal PLL from which all internal clocks are derived. When in external clock mode
(CLKSEL == VDD[7:1]), this input is connected to the DSP clock. Alternatively, a crystal
oscillator can be connected between ZTALI and XTALO.
XTALO — Crystal Oscillator Output
Crystal oscillator output.
CLKSEL — DSP Clock Select
This pin selects the internal source clock. When CLKSEL is low, CLKIN is connected to the
internal PLL from which all internal clocks are derived. When CLKSEL is high, the PLL is
bypassed and the external clock directly drives all input logic.
FDAT7 — DSP AB Bidirectional Data Bus
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
In parallel host mode, these pins provide a bidirectional data bus to DSP AB.
FA0, FSCCLK — Host Parallel Address Bit Zero or Serial Control Port Clock
In parallel host mode, this pin serves as one of two address input pins used to select one of
four parallel registers. In serial host mode, this pin serves as the serial control clock signal,
specifically as the SPI clock input or the
I
2
C
®
clock input.
FA1, FSCDIN — Host Address Bit One or SPI Serial Control Data Input
In parallel host mode, this pin serves as one of two address input pins used to select one of
four parallel registers. In SPI serial host mode, this pin serves as the data input.
FHS1, FRD, FR/W — Mode Select Bit 1 or Host Parallel Output Enable or Host Parallel R/W
DSP AB control port mode select bit 1. This bit is one of 3 control port select bits that are
sampled on the rising edge of RESET to determine the control port mode of DSP AB. In Intel
parallel host mode, this pin serves as the active-low data bus enable input. In Motorola parallel
host mode, this pin serves as the read-high/write-low control input signal. In serial host mode,
this pin can serve as the external memory active-low data-enable output signal.
FHS0, FWR, FDS — Mode Select Bit 0 or Host Write Strobe or Host Data Strobe
DSP AB control port mode select bit 0. This bit is one of 3 control port select bits that are
sampled on the rising edge of RESET to determine the control port mode of DSP AB. In Intel
parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola
parallel host mode, this pin serves as the active-low data-strobe-input signal. In serial host
mode, this pin can serve as the external-memory active-low write-enable output signal.
FCS — Host Parallel Chip Select, Host Serial SPI Chip Select
In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host
SPI mode, this pin is used as the active-low chip-select input signal.
FHS2, FSCDIO, FSCDOUT — Mode Select Bit 2 or Serial Control Port Data Input and Output,
Parallel Port Type Select
DSP AB control port mode select bit 2. This bit is one of 3 control port select bits that are
sampled on the rising edge of RESET to determine the control port mode of DSP AB. In 2-
wire serial mode, this pin serves as the open-drain bidirectional data pin. In SPI mode this pin
serves as the data output pin. In parallel host mode, this pin is sampled at the rising edge of
RESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus.
FINTREQ — Control Port Interrupt Request
Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has
outgoing control data that should be read by the host.
FSCLKN1, STCCLK2 — PCM Audio Input Bit Clock
Digital-audio bit clock input. FSCLKN1 operates asynchronously from all other DSP AB clocks.
In master mode, FSCLKN1 is derived from DSP AB
’s internal clock generator. The active edge
of FSCLKN1 can be programmed by the DSP.
FLRCLKN1 — PCM Audio Input Sample Rate Clock
Digital-audio frame clock input. FLRCLKN1 typically is run at the sampling frequency.
FLRCLKN1 operates asynchronously from all other DSP AB clocks. The polarity of FLRCLKN1
for a particular subframe can be programmed by the DSP.
FSDATAN1 — PCM Audio Data Input One
Digital-audio data input that can accept from one compressed line or 2 channels of PCM data.
FSDATAN1 can be sampled with either edge of FSCLKN1, depending on how FSCLKN1 has
been configured.
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