1-7-2
E59M7BLD
Digital Signal Process Block Diagram
C1
6
D1
8
A1
7
B1
5
E1
4
F1
2
D
V
D-LD
8
CD-LD
10
PD-MONI
7
FS(+)
2
FS(-)
3
TS(+)
1
TS(-)
4
CN201
CN201
CN201
IC201
(SW)
ICS04
(SDRAM)
IC101
(MICR
O CONTR
OLLER)
FS
FS(+)
CLK33M
CD/D
VD
FSEL
FS(-)
TS(+)
TS(-)
TS
DETECT
OR
CD/D
VD
19
Q251,Q252
CD
D
V
D
AMP
Q253,Q254
AMP
4
1
3
6
GND(D
VD-PD)
6
GND(CD-PD)
5
GND(LD)
9
RF
SIGNAL
PR
OCESS
CIRCUIT
DV
D
/C
D
FORMA
TTER
AU
D
IO
I/F
VIDEO
I/F
NTSC/P
AL
ENCODER
DMA
BCU
INST
.
RO
M
32BIT
CPU
DA
T
A
RAM
INTERR
UPT
CONTR
OLLER
W
A
TCH DOG
TIMER
CPU
I/F
TIMER
DECODER
I/F
CPU
I/F
READ
MEMOR
Y
DA
T
A
RAM
DSP
DECODER
I/O
PR
OCESSOR
INST
.
RO
M
DA
T
A
RAM
INST
.
RO
M
SERIAL
D/A
GENERAL
I/O
INTERR
U
PT
CONTR
O
LLER
TIMER
W
A
TCH DOG
TIMER
REMO
TE
CONTR
OL
32BIT CPU
STREAM
I/F
EXTERNAL
MEMOR
Y
I/F
SDRAM
ECC
UMA
C
114
115
116
117
132
131
134
133
129
130
126
124
125
123
83
DEB
U
G
BCU
INST
RAM
DA
T
A
RAM
D/A
D/A
D/A
156
158
Y(I)
C
Pr/R
Pb/B
VIDEO-Y(I)
VIDEO-C
VIDEO-Pr/R
VIDEO-Pb/B
177
SD0/SPDIF
176
SD1
175
SD2
174
SD3
171
SD4
170
SD5
169
SD6
SD0/SPDIF
SD1
SD2
SD3
SD4
SD5
SD6
163
SD7
187
XSHD
186
XSAK
185
SDCK
XSHD
XSAK
SDCK
189
RESET
168
XSRQ
188
SDEF
RESET
XSRQ
SDEF
88
PSP-WCK
55
SA
CD-READ
Y
58
SA
CD-D
A
T
A
PSP-WCK
SA
CD-READ
Y
SA
CD-D
A
T
A
54
SA
CD-LA
TCH
SA
CD-LA
TCH
SA
CD
68
SA
CD
152
151
SDRAM D
A
T
A
(0-31)
SDRAM ADDRESS(0-11)
SDRAM ADDRESS(0-11)
217
238
~
1
18
192
212
252
256
~
~
~
2
13
31
42
45
56
74
85
~
~
~
D
A
T
A(VIDEO/A
UDIO) SIGNAL
VIDEO SIGNAL
D
A
T
A(A
UDIO) SIGNAL
21
27
60
66
~
~
SDRAM D
A
T
A
(0-15)
D/A
149
Y/G
VIDEO-Y/G
181
I/P-SW
I/P-SW
78
ASPECT
ASPECT
PICK-UP
UNIT
T
O
SYSTEM
CONTR
OL/SER
V
O
BLOCK DIA
GRAM
T
O
SA
CD
BLOCK
DIA
GRAM
27MHz
OSC
27MHz
CLOCK
X'T
AL
OSC
CLK
GENE.
X101
D
V
D MAIN CB
A UNIT
T
O
VIDEO
BLOCK
DIA
GRAM
T
O
SA
CD
BLOCK
DIA
GRAM
T
O
A
U
DIO
BLOCK
DIA
GRAM
ICS13
(LA
TCH)
D TYPE
LA
TCH
EXADT (0-15), EADR (16-19)
EXADT (0-15), EADR (16-19)
EXADT (0-7)
EXADT (8-15)
EADR (0-7)
EADR (0-15)
EADR (8-15)
2
9
~
12
19
~
ICS14
(LA
TCH)
D TYPE
LA
TCH
2
9
~
12
19
~
FLASH
RO
M
29
36
38
45
~
~
EXADT (0-15)
EADR (16-19)
~
1
9
16
25
48
~
166
165
69
ICS06
ICS03
4
9
14
1
2
7
~
IC103
(FLASH R
O
M)
+3.3V
(AND GA
TE)
(CLOCK GENERA
T
O
R)
Summary of Contents for DV6500
Page 32: ...1 8 3 1 8 4 E59M7SCD1 DVD Main 1 5 Schematic Diagram ...
Page 33: ...1 8 5 1 8 6 E59M7SCD2 DVD Main 2 5 Schematic Diagram ...
Page 35: ...E59M7SCD3 1 8 9 1 8 10 DVD Main 3 5 Schematic Diagram ...
Page 36: ...E59M7SCD4 1 8 11 1 8 12 DVD Main 4 5 Schematic Diagram ...
Page 37: ...E59M7SCD5 1 8 13 1 8 14 DVD Main 5 5 Schematic Diagram ...
Page 39: ...E59M7SCAV2 1 8 17 1 8 18 AV 2 3 Schematic Diagram ...
Page 41: ...E59M7SCA 1 8 21 1 8 22 5 1ch Amp Schematic Diagram ...
Page 44: ...1 8 27 1 8 28 FUNCTION CBA Top View FUNCTION CBA Bottom View BE5982F01013B ...
Page 45: ...LED CBA Top View LED CBA Bottom View BE5982F01013C 1 8 29 1 8 30 ...
Page 46: ...BE5932F01011 1 8 31 1 8 32 5 1CH AMP CBA Top View 5 1CH AMP CBA Bottom View ...
Page 53: ...1 14 2 E59M7EX Packing X10 X2 X4 S2 S2 S4 Unit S1 X13 X1 A22 X5 X6 A22 ...