
M13-RA6M3-EK_UM - Rev1.0.2
Hardware layout and configuration
M13design - 16 Dec. 21
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2
HARDWARE LAYOUT AND CONFIGURATION
2.1
HARDWARE BLOCK DIAGRAM
Figure 3. Bloc Diagram
UART
JTAG
HEADER
RA6M3
TQFP176
JLINK-OB
24MHz
EXTAL
RGB888
RIIC
4.3-inch
TFT Module
480x272px
CAP TOUCH
PANEL
ETH PHY
RJ45
RMII
USB
Micro-AB
RGB8Bit
RTC
32KHz
FLASH
SPIBSC
SDIO
SDRAM
ADDR/DATA/CTL
EEPROM
RIIC
MODE SEL.
JP2
P201
USBHS
(HOST/DEVICE)
USBFS
(HOST/DEVICE)
U
S
B
CAMERA
Connector
RIIC
3-Axis
MEMS
USER
SW/LED
GPIOS
RST
RESET
SW
RESET
Monitor IC
RST from
JLINK-OB
JTAG
MIKROBUS
SPI/UART
IRQ/GPIOs
PMOD X 2
SPI
IRQ/GPIOs
Audio
Codec
SSIF-2 / RIIC
4-Pole
3.5mm Jack
5V
2.1mm
JACK
DC/DC 1V8
DC/DC 3V3
P
O
W
E
R
JLINK-OB