R7D-CT4E
EM-7802-R Rev.2 P. 5 / 10
DATA ALLOCATION
‘Begin’ address is determined by the R7D’s node address and the master setting.
Analog Input Module
R7D-EA16
Status
CH0
CH1
CH2
CH3
Begin +0
+1
+2
+3
+4
+5
Output Data
Input Data
None
• Example 3. Analog Input R7D-EA16, with Status
Analog Input Module
CH0
CH1
CH2
CH3
Begin +0
+1
+2
+3
Output Data
Analog Input Module
Status
CH0
CH1
CH2
Begin +0
Begin +0
+1
+2
CH3
+3
+4
Output Data
Input Data
None
• Example 1. Analog Input Module, without Status
• Example 2. Analog Input R7D-EC16x, with Status
R7D-EC16x
Input Data
I/O DATA DESCRIPTIONS
0
15
16-bit binary data
Negative values represented in 2
’
s complements
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ANALOG INPUT
0
15
Input 0 (Output 0)
Input 1 (Output 1)
Input 2 (Output 2) 8 points
Input 15 (Output 15)
Input 3 (Output 3)
: : 16 points
Input 7 (Output 7)
Input 8 (Output 8)
: :
0 : OFF
1 : ON
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