Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Interface Guide April 1998
15-12
DRAFT COPY
Lucent Technologies Inc.
15.3 Resetting DSP161X and DSP162X Devices
DSP161X and DSP162X devices have several reset mechanisms. They include powerup reset initiated via an on-
chip powerup reset circuit (PUR), Test Access Port (TAP) Controller reset via the JTAG Test Access Port
1
, device
reset via the RSTB pin of the device, and TAP reset via the TRST pin for the DSP1628/29 only. The proper use and
operation of these reset mechanisms are discussed below.
The two basic types of reset are the TAP Controller reset and the device reset. The TAP Controller reset is per-
formed automatically by the PUR circuit on powerup or by clocking TCK with TMS held high for at least six cycles.
For the DSP1628/29 only, the TAP controller can be reset by asserting the TRST pin low. Because the TAP Con-
troller reset is necessary to ensure control of the device pins, it must be completed before the device reset
sequence can begin.
The device reset is performed by clocking CKI while asserting the external pin RSTB for at least six cycles (twelve
cycles for devices with a 2X CKI rate). The device reset initializes the state of various user registers, synchronizes
the internal clocks, and initiates code execution at location zero of the active memory map. The states of EXM,
INT0, and INT1 during RSTB assertion are sampled by the DSP to determine the behavior of EMI pins and CKO
during reset and the state of the mwait register following reset deassertion.
The methods of asserting the reset mechanisms and their effect on the device are described in the following sec-
tions.
15.3.1 Powerup Reset
All DSP161X and DSP162X devices contain an asynchronous powerup reset circuit that is activated if the device
power supply V
DD
is ramped up according to the device data sheet specification t9. The primary function of the
PUR is to place the device into a state where the DSP can be controlled by external pins. This is achieved by forc-
ing the TAP Controller
2
into the Test Logic Reset (TLR) state.
In the TLR and device reset states, all bidirectional pins are 3-stated and all boundary-scan cells for unidirectional
outputs are cleared. This ensures that on powerup all output enable cells of IC devices in the same JTAG scan
chain have their parallel outputs initialized to an inactive state so that on first entering the boundary-scan instruc-
tions EXTEST or INTEST, the 3-state buses are in the high-impedance state. This prevents logic contention. To
ensure there is no contention on the external memory bus, the external memory interface enable signals are forced
to their inactive state in the TLR state.
15.3.2 Using the TAP to Reset the TAP Controller
Failure to properly reset the device on powerup can lead to a loss of communication with the DSP pins. Because
the TAP is always accessible regardless of the TAP Controller state, an alternate means for putting the TAP Con-
troller into the TLR state and gaining control of the device pins is possible.
As noted in the device data sheets, a power interruption requires that the TAP Controller be reset by the TAP pins
TCK and TMS. Unless internal device nodes are fully discharged, a powerup reset does not properly initialize the
TAP Controller. By clocking TCK through at least six cycles with TMS held high, the TAP Controller will ensure
entry into the TLR state with all the effects described in
Section 15.3.1 . Additionally, the DSP1628/29 can reset the
TAP controller by asserting the TRST pin low. Timing diagrams showing the TAP Controller reset using the TAP
are shown in the respective device data sheets.
These methods of resetting the TAP Controller ensure the user control of the device pins, but TAP Controller resets
will not initialize user accessible portions of the device (i.e., data registers, program counters, etc.). This requires a
device reset through the RSTB pin or a reset by using the Hardware Development System.
1.The JTAG Test Access Port fully conforms to the standards defined in IEEE P1149.1.
2.See Section 11.3.2, The TAP Controller for more information.