Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Hardware Architecture April 1998
2-2
DRAFT COPY
Lucent Technologies Inc.
2.1 Device Architecture Overview
(continued)
2.1.2 Concurrent Operations
Figure 2-2 shows the hardware view of an example of concurrent operations in the device. It also demonstrates the
flexibility of the memory spaces. In this example, the program is executing from the instruction cache. Instructions
are fed directly to the control section freeing the XAB. The program addressing unit (XAAU) is now addressing one
bank of the dual-port RAM (Bank 1) to transfer variable coefficients between the RAM and the DAU. It could alter-
natively have been addressing the ROM to transfer fixed coefficients to the DAU. The data addressing unit (YAAU)
is addressing another bank of the dual-port RAM (Bank 4) to transfer data between the RAM and the DAU. Thus,
in one instruction cycle, two words of data can be transferred to the DAU simultaneously during internal calcula-
tions in the DAU. In the DAU, a multiplication can occur at the same time as an accumulation of a previous
product. In fact, a multiplication can occur in parallel with a variety of ALU operations.
5-4141.a
Figure 2-2. Concurrent Operations in the DSP1611/17/18/27/28/29
CACHE
CONTROL
DUAL-PORT
RAM
BANK 4
DUAL-PORT
RAM
BANK 1
INTERNAL
BUS
YAB
XAB
YDB
XDB
DAU
INSTRUCTIONS
DATA
VARIABLE
COEFFICIENTS
x REGISTER
y REGISTER
MULTIPLIER
ACCUMULATOR
XAAU
YAAU