Lucent Technologies DSP1611, Information Manual, Page: 287 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
JTAG Test Access Port April 1998
11-2
DRAFT COPY
Lucent Technologies Inc.
11.1 Overview of the JTAG Architecture
(continued)
The major subcircuits are as follows:
TAP: For the DSP1611/17/18/27, a four-pin test access port (consisting of input pins—TCK, TMS, and TDI and the
output pin—TDO) provides the standard interface to the test logic. No separate TRST (test logic reset) input pin
exists, but a powerup reset circuit internal to the device resets the TAP Controller to its inactive state if the device is
powered up.
The DSP1628/29 provides a five-pin test access port consisting of the TCK, TMS, TDI, and TDO pins—as in the
DSP1611/17/18/27—plus a TRST (test logic reset input) pin.
TAP Controller: The TAP Controller implements the finite state machine that controls the operation of the test
logic as defined by the standard. The TMS input value sampled on the rising edge of TCK controls the state transi-
tions. The state diagram underlying the TAP Controller is shown in
Figure 11-2 .
5-4130
Note: State transitions are controlled by the value of TMS sampled on the rising edge of TCK.
Figure 11-2. The TAP Controller State Diagram
Instruction Register (JIR): A 4-bit scannable JTAG instruction register with parallel input and parallel output
stages and holds 1 of 16 different instruction codes. The JTAG instructions and their detailed functions are pre-
sented in
Section 11.4, The JTAG Instruction Set . The physical structure of the JIR is covered in Section 11.3.3,
The Instruction Register—JIR .
TEST LOGIC
RESET
RUN-TEST/
SELECT-
SELECT-
CAPTURE-DR
CAPTURE-IR
SHIFT-DR
SHIFT-IR
EXIT1-DR
EXIT1-IR
PAUSE-DR PAUSE-IR
EXIT2-DR
EXIT2-IR
UPDATE-DR UPDATE-IR
1
0
0
1 1
1
0
0
1
0
0
1
1
0
1 0
1
1
0
0
1
0
0
1
1
0
1 0
0
1
1
POWERUP
0
DR-SCAN
IR-SCAN
IDLE