Lucent Technologies DSP1611, Information Manual, Page: 286 / 443

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Lucent Technologies Inc.
DRAFT COPY
11-1
11 The JTAG Test Access Port
The DSP1611, DSP1617, DSP1618, and DSP1627 have a standard four-pin test access port known as JTAG.
The DSP1628, and DSP1629 have a five-pin test access port; the standard four-pin JTAG test access port plus an
additional TRST pin. The test port fully conforms to the standards defined in
IEEE P1149.1
1
. In addition to the
mandatory features of the standard, the JTAG block of the DSP has most of the optional and recommended fea-
tures of the standard. The JTAG block also has custom test data registers and instructions that, with other features
of the device, provide powerful added functions. These are downloading of test programs through the JTAG port
(for self-test purposes) and on-chip support of the hardware development system (on-chip emulation). The full
description of the custom features is beyond the scope of this manual.
An overview of the JTAG architecture follows in Section 11.1 . Section 11.2 is a brief overview of the JTAG instruc-
tions. A more detailed treatment of the material in Section 11.1 and Section 11.2 is found in Section 11.3, Ele-
ments of the JTAG Test Logic , and Section 11.4, The JTAG Instruction Set , respectively.
11.1 Overview of the JTAG Architecture
† Only available on the DSP1628/29.
Figure 11-1. The JTAG Block Diagram
1.The JTAG port of the DSP has successfully passed the IEEE P1149.1 protocol certification test sequence generated by TAPDANCE

, which
is a rigorous, implementation independent test package developed and administered by Lucent Technologies.
TDI
TMS
TCK
TDO
TAP
TCK
TMS
POWERUP RESET
jtag
JCON
JBPR
JIDR
JBSR
INSTRUCTION DECODER
JIR
JTAG
OUTPUT
STAGE
(JOUT)
TDI
IR CONTROLS
TDI
TA
P
C
O
NT
RO
L
L
E
R
TEST DATA
REGISTERS
DR
CONTROLS
JSTATUS
TDO
TRST †
TRST
†