Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Serial I/O April 1998
7-4
DRAFT COPY
Lucent Technologies Inc.
7.1 SIO Operation
(continued)
7.1.2 Input Section
Figure 7-4 shows the timing relationships for the SIO input port signals in passive mode (passive mode is defined
here as ILD being supplied by an external device). A typically free-running bit clock (ICK) synchronizes all events
occurring within the input section of the SIO. A high-to-low transition of the input load (ILD) signal followed by the
next rising edge of ICK initiates the start of an input transaction. The first serial data bit is read from DI on the next
rising edge of ICK. Eight bits or 16 bits later (depending on the word size selected by the sioc ILEN field) if the
input shift register (isr) fills, this data is transferred to the input buffer register (sdx[IN]). At this time, the input buffer
full (IBF) flag and signal are also asserted indicating that the buffer is full. If enabled, the IBF interrupt will become
pending. The DSP device can read the data at this time. The read command is of the type a0 = sdx, a1 = sdx,
or Y = sdx (see
Section 4.5.3, Data Move Instructions ). The IBF flag and signal are negated when the input buffer
is read synchronized with a rising edge of CKO. Another serial input can begin before the input buffer read takes
place because the port is double-buffered. If the new transfer is completed before the previous input is read, the
new data is transferred to the other input buffer overwriting the old data.
Figure 7-4 also shows how back-to-back
reads are pipelined.
5-4174
Figure 7-4. SIO Passive Mode Input Timing, 16-bit Words
ILD
IBF
CKO
a0 = sdx
ICK
B0 B2 B3 B1
DI
LATCH
B15 B0 B1