Lucent Technologies DSP1611, Information Manual

Page: 170 / 443

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Core Architecture
Lucent Technologies Inc.
DRAFT COPY
5-15
5.3 Y Address Arithmetic Unit (YAAU)
(continued)
5.3.4 Addressing Modes (continued)
Direct Data Addressing
Figure 5-7 describes direct data addressing. The upper 11 bits of the address are held in the upper portion of the
ybase register (labelled BASE in Figure 5-7 ). If a data move instruction using direct data addressing is executed
(see Section 4.3.3, Direct Data Addressing ), the instruction contains 4 bits selecting one of 16 registers (e.g., r0 or
a0) as the source or destination for the data move and 5 bits that form the offset part of the address. The five offset
bits are concatenated to the 11 base bits to form an address. The corresponding location becomes a source or
destination for the data move.
5-4160
Figure 5-7. Direct Data Addressing
11
5
5
RAM
REGISTER DR
BASE
ybase
REGISTER
IN YAAU
CONTROL
T-FIELD
DR SPECIFIED
1
OFFSET
16
16
0 4 5 15
15 10 9 5 4 0 6
YAB
YDB
16
OFFSET
XDB
INSTRUCTION
iN X-MEMORY
SPACE
DR = *(OFFSET)
or
*(OFFSET) = DR
16
5
11
R/W