LSI LSI53C896, Technical Manual

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1-6 Introduction
world cabling environments. TolerANT technology is compatible with both
the Alternative One and Alternative Two termination schemes proposed
by the American National Standards Institute.
1.5 LSI53C896 Benefits Summary
This section provides an overview of the LSI53C896 features and
benefits. It contains information on
SCSI Performance , PCI Performance ,
Integration , Ease of Use , Flexibility , Reliability , and Testability .
1.5.1 SCSI Performance
•
Has integrated LVDlink universal transceivers which:
– Support SE, LVD, and HVD signals (with external transceivers).
– Allow greater device connectivity and longer cable length.
– LVDlink transceivers save the cost of external differential
transceivers.
– Supports a long-term performance migration path.
•
With a 944 byte FIFO, the chip can efficiently burst up to 512 bytes
across the PCI bus.
•
Two separate SCSI channels on one chip.
•
Performs wide, Ultra2 SCSI synchronous transfers as fast as
80 Mbytes/s on each SCSI channel for a total of 160 Mbytes/s.
•
Can handle phase mismatches in SCRIPTS without interrupting the
system processor.
•
On-chip SCSI clock quadrupler allows the chip to achieve Ultra2
SCSI transfer rates with an input frequency of 40 MHz.
•
Includes 8 Kbytes of internal RAM for SCRIPTS instruction storage
for each SCSI channel.
•
31 levels of SCSI synchronous offset.
•
Supports variable block size and scatter/gather data transfers.
•
Performs sustained memory-to-memory DMA transfers to
approximately 100 Mbytes/s.
•
Minimizes SCSI I/O start latency.
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