LSI LSI53C896, Technical Manual

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LSI53C896 Benefits Summary 1-9
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Programs local and bus flash memory.
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Selectable 112 or 944 byte DMA FIFO for backward compatibility.
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Tailored SCSI sequences execute from main system RAM or internal
SCRIPTS RAM.
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Flexible programming interface to tune I/O performance or to adapt
to unique SCSI devices.
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Support for changes in the logical I/O interface definition.
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Low level access to all registers and all SCSI bus signals.
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Fetch, Master, and Memory Access control pins.
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Separate SCSI and system clocks.
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SCSI clock quadrupler bits enable Ultra2 SCSI transfer rates with a
40 MHz SCSI clock input.
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Selectable IRQ pin disable bit.
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Ability to route system clock to SCSI clock.
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Compatible with 3.3 V and 5 V PCI.
1.5.6 Reliability
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2 kV ESD protection on SCSI signals.
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Protection against bus reflections due to impedance mismatches.
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Controlled bus assertion times (reduces RFI, improves reliability, and
eases FCC certification).
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Latch-up protection greater than 150 mA.
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Voltage feed-through protection (minimum leakage current through
SCSI pads).
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More than 25% of pins are power and ground.
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Power and ground isolation of I/O pads and internal chip logic.
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TolerANT technology provides:
– Active negation of SCSI Data, Parity, Request, and Acknowledge
signals for improved fast SCSI transfer rates.
– Input signal filtering on SCSI receivers improves data integrity,
even in noisy cabling environments.
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