LSI LSI53C895A, Technical Manual

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4-108 Registers
4.4 Phase Mismatch Jump Registers
Eight 32-bit registers contain the byte count and addressing information
required to update the direct, indirect, or table indirect BMOV instructions
with new byte counts and addresses. The eight register descriptions
follow.
All registers can be read/written using the Load and Store SCRIPTS
instructions, Memory-to-Memory Moves, read/write SCRIPTS
instructions, or the CPU with SCRIPTS not running.
Registers: 0xC0–0xC3
Phase Mismatch Jump Address 1 (PMJAD1)
Read/Write
PMJAD1 Phase Mismatch Jump Address 1 [31:0]
This register contains the 32-bit address that will be
jumped to upon a phase mismatch. Depending upon the
state of the PMJCTL bit in register
Chip Control 0
(CCNTL0) this address will either be used during an
outbound (data out, command, message out) phase
mismatch (PMJCTL = 0) or when the WSR bit is cleared
(PMJCTL = 1). It should be loaded with an address of a
SCRIPTS routine that will handle the updating of memory
data structures of the BMOV that was executing when the
phase mismatch occurred.
31 0
PMJAD1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0