LSI LSI53C1000, Technical Manual

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Memory Move Instructions 5-35
Figure 5.12 Memory Move Instructions - First Dword
IT[2:0] Instruction Type - Memory Move [31:29]
R Reserved [28:25]
These bits are reserved and must be zero. If any of these
bits are set, an illegal instruction interrupt occurs.
NF No Flush 24
When this bit is set, the LSI53C1000 performs a Memory
Move without flushing the prefetch unit. When this bit is
cleared, the Memory Move instruction automatically
flushes the prefetch unit. Use the No Flush option if the
source and destination are not within four instructions of
the current Memory Move instruction.
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For information on
SCRIPTS instruction prefetching, see Chapter 2, “Func-
tional Description.”
TC[23:0] Transfer Count [23:0]
The number of bytes to transfer is stored in the lower
24 bits of the first instruction word.
5.6.1 Read/Write System Memory from a SCRIPT
By using the Memory Move instruction, single or multiple register values
are transferred to or from system memory.
Because the LSI53C1000 responds to addresses as defined in the Base
Address Register Zero (BAR0) (I/O) or Base Address Register One
(BAR1) (MEMORY) registers, the device can be accessed during a
Memory Move operation if the source or destination address decodes to
within the chip’s register space. If this occurs, the register indicated by
the lower seven bits of the address is taken as the data source or
destination. In this way, register values are saved to system memory and
later restored, and SCRIPTS can make decisions based on data values
in system memory.
31 29 28 25 24 23 16 15 8 7 0
DCMD Register DBC Register
IT[2:0] R NF TC[23:0]