4/29/2020
Loongson 3A3000 / 3B3000 Processor User Manual
53
61
1
–
Doubleword
bit 1: Don't Care
bit 0: Don't Care
1 – Doubleword
bit 1: Don't Care
bit 0: must be 1
01xxxx
NPC
Read
bit 3: Don't Care
bit 2: 0 – Byte
1
–
Doubleword
bit 1: Don't Care
bit 0: Don't Care
bit 3: Don't Care
bit 2: 0 – Byte
1 – Doubleword
bit 1: Don't Care
bit 0: must be 1
110000
R
RdRespons
e
Read operation returns
110011
R
TgtDone
Write operation returns
110100
PC
WrCoherent
----
Write command extension
110101
PC
WrAddr
----
Write address extension
111000
R
RespCohere
nt
----
Read response extension
111001
NPC
RdCoherent
----
Read command extension
111010
PC
Broadcast
No operation
111011
NPC
RdAddr
----
Read address extension
111100
PC
FENCE
Guaranteed order relationship
111111
-
Sync / Error
Sync / Error
For the sending end, the commands sent out in the two modes are shown in the following table.
Table 10- 3 Commands to be sent out in two modes
coding
aisle
command
Standard mode
Extension (consistency)
000000
-
NOP
Empty package or flow control
x01x0x
NPC
or
Write
bit 5: 0-Nonposted
1-Posted
bit 5: Must be 1, POSTED
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Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
PC
bit 2: 0 – Byte
1 – Doubleword
bit 0: must be 0
bit 2: 0 – Byte
1 – Doubleword
bit 0: must be 1
010x0x
NPC
Read
bit 2: 0 – Byte
1 – Doubleword
bit 0: Don't Care
bit 2: 0 – Byte
1 – Doubleword
bit 0: must be 1
110000
R
RdResponse
Read operation returns
110011
R
TgtDone
Write operation returns
110100
PC
WrCoherent
----
Write command extension
110101
PC
WrAddr
----
Write address extension
111000
R
RespCoherent
----
Read response extension
111001
NPC
RdCoherent
----
Read command extension
111011
NPC
RdAddr
----
Read address extension
111111
-
Sync / Error
Will only forward
10.3 HyperTransport interrupt support
The HyperTransport controller provides 256 interrupt vectors, which can support Fix, Arbiter and other types of interrupts.
However, there is no support for hardware automatic EOI. For the above two supported types of interrupts, the controller will
Automatically write to the interrupt register, and perform interrupt notification to the system interrupt controller according to the setting of the interrupt mask register. With
For the body's interrupt control, please see the interrupt control register set in Section 10.5.8.
In addition, the controller provides special support for PIC interrupts to speed up this type of interrupt processing.
A typical PIC interrupt is completed by the following steps:
①
The PIC controller sends a PIC interrupt request to the system;
②
The system
Send the interrupt vector query to the PIC controller;
③
The PIC controller sends the interrupt vector number to the system;
④
The system clears the PIC controller
The corresponding interrupt on the controller. Only after the above four steps are completed, the PIC controller will issue the next interrupt to the system. for
Loongson 3A3000 / 3B3000 HyperTransport controller will automatically perform the first three steps of processing and interrupt the PIC to
Write the corresponding position in the 256 interrupt vectors. After the software system has processed the interrupt, it needs to go to step 4.
Management, that is, to issue a clear interrupt to the PIC controller. After that, the process of the next interrupt is started.