background image

9

LT1010

1010fc

be unrealistic to use these worst-case numbers above
because paralleled units are operating under identical
conditions. The offset voltage specified for V

S

 = 

±

15V,

V

IN

 = 0V and T

A

 = 25

°

C will suffice for a worst-case

condition.

APPLICATIO  S I  FOR   ATIO

W

U

U

U

At lower frequencies, the buffer is within the feedback loop
so that its offset voltage and gain errors are negligible. At
higher frequencies, feedback is through C

F

, so that phase

shift from the load capacitance acting against the buffer
output resistance does not cause loop instability.

Stability depends upon the R

F

C

F

 time constant or the

closed-loop bandwidth. With an 80kHz bandwidth, ring-
ing is negligible for C

L

 = 0.068

µ

F and damps rapidly for

C

L

 = 0.33

µ

F. The pulse response is shown in the graph.

A1

LT1010

V

IN

V

A2

LT1010

V

+

I

S

I

OUT

I

I

OUT

I

– 

I

OUT

V

OUT

1010 AI03

I

S

A2

LT1010

R

S

R

F

20k

V

IN

C

F

100pF

C

L

1010 AI04

V

OUT

+

A1

LT1007

Output load current will be divided based on the output
resistance of the individual buffers. Therefore, the avail-
able output current will not quite be doubled unless output
resistances are matched. As for offset voltage, the 25

°

C

limits should be used for worst-case calculations.

Parallel operation is not thermally unstable. Should one
unit get hotter than its mates, its share of the output and
its standby dissipation will decrease.

As a practical matter, parallel connection needs only some
increased attention to heat sinking. In some applications,
a few ohms equalization resistance in each output may be
wise. Only the most demanding applications should re-
quire matching, and then just of output resistance at 25

°

C.

Isolating Capacitive Loads

The inverting amplifier below shows the recommended
method of isolating capacitive loads. Noninverting ampli-
fiers are handled similarly.

TIME (

µ

s)

0

OUTPUT VOLTAGE (V)

0

200

1010 AI05

0

50

100

150

5

–5

–5

5

C

L

 = 0.068

µ

F

C

L

 = 0.33

µ

F

Pulse Response

Small-signal bandwidth is reduced by C

F

, but consider-

able isolation can be obtained without reducing it below
the power bandwidth. Often, a bandwidth reduction is
desirable to filter high frequency noise or unwanted
signals.

A2

LT1010

R

F

2k

R

S

2k

V

IN

C

F

1nF

C

L

1010 AI06

V

OUT

+

A1

LT118A

The follower configuration is unique in that capacitive
load isolation is obtained without a reduction in small-
signal bandwidth, although the output impedance of the
buffer comes into play at high frequencies. The precision
unity-gain buffer above has a 10MHz bandwidth without
capacitive loading, yet it is stable for all load capacitance
to over 0.3

µ

F, again determined by R

F

C

F

.

Summary of Contents for LT1010

Page 1: ...h 75V s Slew Rate Drives 10V into 75 5mA Quiescent Current Drives Capacitive Loads 1 F Current and Thermal Limit Operates from Single Supply 4 5V Very Low Distortion Operation Available in 8 Pin miniD...

Page 2: ...20 mV VS 15V VIN 0V 20 100 mV IB Input Bias Current IOUT 0mA 0 250 A IOUT 150mA 0 500 A 0 800 A AV Large Signal Voltage Gain 0 995 1 00 V V ROUT Output Resistance IOUT 1mA 5 10 IOUT 150mA 5 10 12 Slew...

Page 3: ...e DD package for ambient temperatures above 25 C See Applications Information Note 3 In current limit or thermal limit input current increases sharply with input output differentials greater than 8V s...

Page 4: ...0 50 150 10 20 1010 G04 30 100 RL 100 TJ 25 C INPUT OUTPUT FREQUENCY MHz 0 1 1 OUTPUT IMPEDANCE 10 100 1 10 100 1010 G05 IBIAS 0 TJ 25 C FREQUENCY MHz 0 1 20 VOLTAGE GAIN dB 0 10 1 10 100 1010 G06 10...

Page 5: ...utput Noise Voltage TEMPERATURE C 50 0 997 GAIN V V 0 998 0 999 0 50 100 150 1010 G13 1 000 IOUT 0 VS 40V VS 4 5V TEMPERATURE C 50 0 OUTPUT RESISTANCE 4 8 0 50 100 150 1010 G14 12 2 6 10 IOUT 150mA FR...

Page 6: ...0 1 0 RL 50 f 10kHz VS 15V TC 25 C IBIAS 0 RBIAS 50 FREQUENCY kHz 1 0 4 HARMONIC DISTORTION 0 6 0 8 10 100 1000 1010 G21 0 2 0 IBIAS 0 VS 15V VOUT 10V TC 25 C RL 50 RL 100 Shorted Input Characteristic...

Page 7: ...84 2See electrical characteristics section for guaranteed limits The scheme is not perfect in that the rate of rise of sink current is noticeably less than for source current This can be mitigated by...

Page 8: ...st case over a range of supply voltages input voltage and temperature It would groundplaneisprudent especiallywhenoperatingathigh frequencies Thebufferslewratecanbereducedbyinadequatesupply bypass Wit...

Page 9: ...tions Parallel operation is not thermally unstable Should one unit get hotter than its mates its share of the output and its standby dissipation will decrease Asapracticalmatter parallelconnectionneed...

Page 10: ...ve loads is determined by RFCF Wideband Amplifiers This simple circuit provides an adjustable gain video amplifier that will drive 1VP P into 75 The differential pair provides gain with the LT1010 ser...

Page 11: ...rrent Sources A standard op amp voltage to current converter with a buffer to increase output current is shown here As usual A3 LT1010 A2 LT1010 R2 200 R1 50 R3 800 R4 39 R5 39 C1 20pF INPUT 1010 AI11...

Page 12: ...ent to A3 Supply Splitter Dual supply op amps and comparators can be operated fromasinglesupplybycreatinganartificialgroundathalf the supply voltage The supply splitter shown here can source or sink 1...

Page 13: ...ansfer function This circuit is somewhat similar except that the Q2 Q3 stage takes gain A2 DC stabilizes the input output path and A1 provides drive capability Feedback is to Q2 s emitter from A1 s ou...

Page 14: ...A 0 2V DIV B 0 2V DIV 1010 AI20 1010 AI21 Figures A and B show response with both output stages The LT1010 is used in Figure A Trace A input Trace B output Figure B uses the discrete stage and is slig...

Page 15: ...perating tempera ture of the device Thermal Resistance of DFN Package For surface mount devices heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper tra...

Page 16: ...output saturation voltage with no load Saturation Resistance The ratio of the change in output saturation voltage to the change in current producing it going from no load to full load Slew Rate The av...

Page 17: ...INCLUDE MOLD FLASH MOLD FLASH IF PRESENT SHALL NOT EXCEED 0 15mm ON ANY SIDE 5 EXPOSED PAD SHALL BE SOLDER PLATED 6 SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 0 3...

Page 18: ...5 3 302 0 127 020 0 508 MIN 018 003 0 457 0 076 120 3 048 MIN 1 2 3 4 8 7 6 5 255 015 6 477 0 381 400 10 160 MAX 008 015 0 203 0 381 300 325 7 620 8 255 325 035 015 0 889 0 381 8 255 NOTE 1 DIMENSIONS...

Page 19: ...T Package 5 Lead Plastic TO 220 Standard Reference LTC DWG 05 08 1421 U PACKAGE DESCRIPTIO T5 TO 220 0801 028 038 0 711 0 965 067 1 70 135 165 3 429 4 191 700 728 17 78 18 491 045 055 1 143 1 397 095...

Page 20: ...dback Amplifier 900V s Slew Rate Stable with Large Capacitive Loads LT1795 Dual 500mA 50MHz CFA 500mA IOUT ADSL Driver LT1886 Dual 700MHz 200mA Op Amp DSL Driver LINEAR TECHNOLOGY CORPORATION 1991 LT...

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