6
Rev. 0
JUMPER FUNCTIONS
JUMPER DEFAULT
NAME
DESCRIPTION
JP1
On
isoSPI Term
Enable/disable 100e isoSPI bus termination.
If LTC2949 is the only device on the isoSPI bus or
connected on top of a cell monitor isoSPI daisy chain, the termination must be enabled. If LTC2949 is
connected in parallel to a daisy chain (LTC2949 is fed into the input of a daisy chain via J1, J2) of cell
monitors, the termination must be disabled.
JP2
EN
Auto Sleep
Enable/disable automatic entering of sleep state after power-up.
The LTC2949 automatically returns
to sleep state if no wake-up confirmation command is received within 1 second after entering standby
state, after power-up. Wake-up confirmation can be either writing 0x00 to register 0x70 or starting of
a measurement. LTC2949 will not go automatically to sleep if SDA is pulled low (JP2 at position DIS)
during power-up. As SDA is also used for the optional external EEPROM, it must be released from GND
to allow communication to the EEPROM. In most applications, the Auto Sleep will stay enabled and the
muster will send the wake-up acknowledge. Still, for debugging purposes, this jumper may be set to DIS
to force LTC2949 to stay in standby mode.
JP3–JP6
isoSPI
SPI/isoSPI
Select between nonisolated SPI or isolated isoSPI communication mode.
All jumpers must be either
set to the left (SPI) or the right (isoSPI) position. In case the QuikEval™ connector J4 is connected to a
Linduino, the interface must be set to SPI.
JP7, JP8
Low
High/
Low Side
Select between high or low side current sensing.
To avoid the sense resistor being floating, it can be
tight to either LTC2949’s GND (low side sensing) or to LTC2949’s A/DV
CC
(high side sensing). It is also
possible to remove both jumpers (or set JP7 to low and JP8 to high) if the shunt is applied somewhere
between LTC2949’s supply rails by external connections. See following sections for example setups.
JP9
EN
PWR
Enable/disable the onboard flyback converter LT8301
. The isolated onboard supply can also be
disabled by disconnecting V
CC
, LGND or setting V
CC
, LGND to less than 3V (see V
UVLO
–).
JP10
7V
ADV
CC
Enable (7V)/disable (off) connection of LTC2949’s A/DVCC supply input to V
+
of J4.
If Linduino is
connected to J4, V
+
is supplied with 7V from a SMPS with post LDO on the Linduino. The Linduino
allows to override this voltage up to LTC2949’s max. operating voltage of 14.5V via turrets ADV
CC
and
GND. If JP10 is set to off, it is also possible to apply any voltage between 4.5V and 14.5V to ADV
CC
and
still use the Linduino connected via J4.
JP11
5.3V
V
OUT
Onboard isolated flyback converter LT8301 output voltage selector.
Select one of three (5.3V, 9.0V,
12.4V) pre-configured output voltages for the flyback converter. Higher supply voltages are useful to
take advantage of LTC2949’s GPOs being able to drive the output to one of LTC2949’s supply rails. This
allows for example to ensure sufficient gate-source voltage when using MOSFETs to switch high voltage
resistive dividers connected to LTC2949’s voltage inputs. See Hardware Setup Examples section and
LTC2949 data sheet for more details.
HARDWARE DESCRIPTION
